BELK-AN-001: Asymmetric Multiprocessing (AMP) on Bora – Linux FreeRTOS

Info Box Applies to Bora Applies to BORA Xpress

History

Version	Date	BELK version	Notes
1.0.0	November 2013	1.1.0	First release
1.0.1	November 2013	1.1.0	Added UART0 pinout information Minor fixes
1.1.0	November 2013	1.1.0	Added support for RPMsg example
1.5.0	December 2013	1.1.0	Added chapter related to Lauterbach debugger
1.5.1	January 2014	1.1.0	Minor fixes
1.6.0	April 2014	2.0.0	Minor fixes Updated for BELK 2.0.0 release

Introduction

This application note describes how to build the software components required to set up asymmetric multi-processing (AMP for short) configuration required to run Linux OS on first Cortex-A9 core and FreeRTOS on second Cortex-A9 core of the Zynq SOC.

Asymmetric Multiprocessing (AMP) allows a multiprocessor/multicore system to run multiple Operating Systems (OS) that are independent of each other. In other words, each CPU has its own private memory space, which contains the OS and the applications that are to run on that CPU. In addition, there can be some shared memory space that is used for multiprocessor communication. This is contrasted with Symmetric Multiprocessing (SMP), in which one OS runs on multiple CPUs using a public shared memory space. Thanks to AMP, developers can use open-source Linux and FreeRTOS operating systems and the RPMsg Inter Processor Communication (IPC) framework between the Zynq's two high-performance ARM® Cortex™-A9 processors to quickly implement applications that need to deliver deterministic, real-time responsiveness for markets such as automotive, industrial and others with similar requirements. For further information, please refer to this link.

Two different examples are here provided. The first one – HelloWorld – shows basic functionalities while the second – RPMsg-based application – exploits more sophisticated techniques to handle inter-processors communication and synchronization. This latter configuration is based on RPMsg mechanism as described in Xilinx document UG978 (v2013.04, April 22, 2013).

PDF version of this Application Note can be downloaded here.

AMP on Bora

The following sections detail how to build the software components required to set up asymmetric multi-processing (AMP for short) configuration required to run Linux OS on first Cortex-A9 core and FreeRTOS on second Cortex-A9 core. The prerequisites are:

• Vivado® Design Suite version 2013.3 with Xilinx SDK (Webpack license is minimum requirements)
• Python 2.7.x (C:\Python27 must be the installation directory on Windows)
• Bora Embedded Linux Kit (Please refer to BELK Quick Start Guide for further details) version 2.0.0.
• BORA FreeRTOS repository (please refer to section TBD)

Building the software components

Vivado project

• log into the development host
• Assuming that a local repository has not been created, clone the remote Bora git repository (the -b option is used to automatically checkout the current branch):

git clone git@git.dave.eu:dave/bora/bora.git -b bora

• Enter the git directory
• Switch to bora branch (not required if this is already the current branch):

git checkout bora

Set project directory variable:

export PROJ_DIR=$(pwd)/../bora-build-YYYYMMDD-nobk

Configure Vivado settings (1):

. /opt/Xilinx/Vivado/2013.3/settings64.sh

Launch Vivado with build_project script (2):

vivado -mode tcl -source build_project.tcl -notrace -tclargs "-bitstream"

(1) In a 32 bit system, Vivado settings are configured with the following command /opt/Xilinx/Vivado/2013.3/settings32.sh

(2) Passing the -tclargs "-bitstream" parameters allows for automatic building of the FPGA bitstream.

FSBL

Once the Vivado project build is completed, the hardware configuration can be exported starting the SDK to build the FSBL. From the SDK GUI:

• Create a new application project, as shown in the picture below:

• Configure the application settings as shown in the pictures below:

• Click finish to launch FSBL build process
• Create the binary from the FSBL ELF chosing one of the following options:
  • manually launch the command: arm-xilinx-eabi-objcopy -v -O binary $PROJ_DIR/bora.sdk/SDK/SDK_Export/bora_FSBL/Debug/bora_FSBL.elf $PROJ_DIR/bora.sdk/SDK/SDK_Export/bora_FSBL/Debug/bora_FSBL.bin
  • configure the automatic binary generation on project build. In Project Explorer, right-click on bora_FSBL project and select C/C++ Build Settings and add the command arm-xilinx-eabi-objcopy -v -O binary ${ProjName}.elf ${ProjName}.bin on Post-build steps

N.B. When the Vivado project is modified, the binary must be re-generated with the following command:

python fpga-bit-to-bin.py --flip $PROJ_DIR/bora.runs/bora_run_impl/bora_design_wrapper.bit $PROJ_DIR/bora.runs/bora_run_impl/bora_design_wrapper.bin

FreeRTOS applications

The following sections describe the steps required to configure and build both the Helloworld and the RPMsg-based examples.

Importing the FreeRTOS repository into the SDK

• Assuming that a local repository has not been created, clone the remote FreeRTOS git repository:

git clone git@git.dave.eu:dave/bora/freertos.git

• Enter the git directory
• Switch to freertos-AMP branch:

git checkout freertos-AMP

• In SDK gui import new repository: Xilinx Tools->Repositories

• Click New... to add a new repository under Local or Global Repositories, and select the freeRTOS repository directory:

• Click Rescan Repositories , Apply and OK
• At the end of the procedure, applications based on freeRTOS operating system can be built

Documentation

Please download the application note in PDF format.

Additional resources

• http://www.wiki.xilinx.com/Multi-OS+Support+%28AMP+%26+Hypervisor%29
• http://www.xilinx.com/support/documentation/sw_manuals/petalinux2013_04/ug978-petalinux-zynq-amp.pdf