3,260
edits
Changes
m
|}Please refer to the carrier board schematics for details on center tabs connection.
→Ethernet port ETH - J6
!Notes
|-
|1 11 || ETH0_TXRX0_P || - || -
|-
|2 10 || ETH0_TXRX0_M || - || -
|-
|3 4 || ETH0_TXRX1_P || - || -
|-
|4 3 || ETH0_TXRX2_P || - || -
|-
|5 2 || ETH0_TXRX2_M || - || -
|-
|6 5 || ETH0_TXRX1_M || - || -
|-
|7 8 || ETH0_TXRX3_P || - || -
|-
|8 9 || ETH0_TXRX3_M || - || -
|-
|9 15 || NVCC_AXEL_I/O_3.3V/1.8V ETH0_LED1 || - || -
|-
|10 13 || ETH_SH ETH0_LED2 || - || -
|-
|1117, 13 || NVCC_AXEL_I/O_3.3V/1.8V || - || -|-|12 || ETH0_LED1 || - || -|-|14 || ETH0_LED2 || - || -|-|15, 16 18 || ETH_SH || - || -
|-
|}
=== PCI Express - J7 ===