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==Introduction==
Reset scheme is strictly related to power supply unit. As such, reading of [[Power_Power (AXELULiteAXEL ULite)|this page]] is strongly recommended.
== Reset scheme and control signals ==
Some signals that are related to reset circuitry are pulled-up to VDD_SNVS_IN. This voltage is generated by PMIC PF3000's VSNVS LDO/Switch and its actual value depends on:
* voltage applied to PF3000 VIN pin
** in case of AXELULite AXEL ULite this pin is connected to VIN_SOM power rail
* voltage applied to PF3000 LICELL pin
** in case of AXELULite AXEL ULite this pin is connected to pin 14 of SODIMM connector (PMIC_LICELL).
Hence '''it is recommended that system designer takes into account these factors in order to properly manage these signals at carrier board level'''.
=== Handling CPU-initiated software reset ===
By default, iMX6UL processor does not assert any external signal when it initiates a software reset sequence. This might not guarantee a safe system reset in all conditions. For these reasons, AXELULite AXEL ULite integrates a specific circuit that, in combination with the use on iMX6UL watchdog timer (WDT), guarantees a full hardware reset in case a software reset is issued. It is worth remembering that when this reset is triggered, a full power up cycle is issued. This technique makes use of the GPIO1_IO08 pin. Particular attention needs to be paid in case this pin needs to be used at carrier board level as well. For more details please contact the [mailto:support-axel@dave.eu technical support].
This technique is supported by [[AXELULite_and_SBC_Lynx_Embedded_Linux_Kit_AXEL ULite and SBC Lynx Embedded Linux Kit (XUELK)|AXELULite AXEL ULite Embedded LinuxKit]].
==References==
{{reflist}}
