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<section begin="History" />{| style="border-collapse:collapse; "! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History|- ! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes|-| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |{{InfoBoxTopoldid|5204|2016/07/21}}| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |New documentation layout|-| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |{{AppliesToAXELULiteoldid|7028|2017/08/04}}{{InfoBoxBottom}| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Add PMIC_PWRON information|-! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |2020/10/15! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |Minor changes|}<section end="History" />__FORCETOC__<section begin="Body" />
== Reset scheme and control signals ==
Reset scheme is strictly related to power supply unit. As such, reading of [[Power (AXEL ULite)|this page]] is strongly recommended.
The following picture shows the simplified block diagram of reset scheme and voltage monitoring.
[[File:AXELULite-reset-scheme.png|thumb|center|600px|Simplified block diagram of reset circuitry and voltage monitoring]]
=== PMIC_VSNVS VDD_SNVS_IN ===Some signals that are related to reset circuitry are pulled-up to PMIC_VSNVSVDD_SNVS_IN. This voltage is generated by PMIC PF0100PF3000's VSNVS LDO/Switch and its actual value depends on:* voltage applied to PMICS's PF3000 VIN pin** in case of AxelLite AXEL ULite this pin is connected to 3.3VIN VIN_SOM power rail* voltage applied to PMICS's PF3000 LICELL pin** in case of AxelLite AXEL ULite this pin is connected to pin 14 of SODIMM connector (PMIC_LICELL)* PMIC's VSNVSCTL register configuration.
Hence '''it is recommended that system designer takes into account these factors in order to properly manage these signals at carrier board level'''.
For more details please refer to section ''VSNVS LDO/Switch'' of ''MMPF0100 Freescale Semiconductor PF3000 Advance Information'' document<ref name="PF3000">Freescale Semiconductor, ''PF3000 Advance Information - Power Management Integrated Circuit (PMIC) for i.MX 7 & i.MX 6SL/SX/UL''</ref>.
=== CPU_PORn ===
The following devices can assert this active-low signal:
* PMIC
* multiple-voltage monitor: this device monitors critical power voltages and triggers a reset pulse in case any of these exhibits a brownout condition .
Since SPI NOR flash can be used as boot device, CPU_PORn is connected to this device too. This guarantees it is in a known state when reset signal is released.
=== Handling CPU-initiated software reset ===
By default, iMX6UL processor does not assert any external signal when it initiates a software reset sequence. This might not guarantee a safe system reset in all conditions. For these reasons, AXEL ULite integrates a specific circuit that, in combination with the use on iMX6UL watchdog timer (WDT), guarantees a full hardware reset in case a software reset is issued. It is worth remembering that when this reset is triggered, a full power up cycle is issued. This technique makes use of the GPIO1_IO08 pin. Particular attention needs to be paid in case this pin needs to be used at carrier board level as well. For more details please contact the [mailto:support-axel@dave.eu technical support].
This technique is supported by [[AXEL ULite and SBC Lynx Embedded Linux Kit (XUELK)|AXEL ULite Embedded LinuxKit]].
==== Forcing a software reset using an external signal ====
As described before, GPIO1_IO08 is used by internal watchdog for triggering a software reset using [[Pinout_(AXEL_ULite)#PMIC_PWRON|PMIC_PWRON]].
The same input signal, can be used with an external push-button for triggering a software reset too.
[[Pinout_(AXEL_ULite)#PMIC_PWRON|PMIC_PWRON]] has an internal pull-up (see [[Reset_scheme_(AXEL_ULite)#Reset_scheme_and_control_signals|Reset scheme]]) and must be driven with an open-drain signal === Handling CPU-initiated software reset References==='''By default, MX6 processor does not assert any external signal when it initiates a software reset sequence. Also default software reset implementation does not guarantee that all processor registers are reset properly'''. For these reasons, it is strongly recommended to use a different approach that, in combination with the use of a processor's watchdog timer (WDT), provides a full hardware reset in case a software reset is issued.{{reflist}}