AXEL ULite SOM/AXEL ULite Hardware/Power and Reset/Power Supply Unit (PSU) and recommended power-up sequence

Info Box Applies to AXEL ULite

Introduction

AXEL ULite system-on-module (SOM for short) is powered by carrier board via VIN_SOM rail.

About voltage range, three supported configurations are available. These configurations are indicated by the value of the f field of the ordering code. The generic ordering code is in the form:

DA p l r n c f t s

The field f can assume the following values:

• 0, 1: power supply voltage range 3.135 - 3.465V (that is 3V3±5%)
• 2: power supply voltage range is 3.3 - 4.5V
  • please note that this range can be widened by the use of an external MOSFET; for more details please refer to technical support
• 3: power supply voltage range is 3.25 - 3.465V (that us 3.3 +5%/-1.5%).

Voltage references for single-ended I/O signals the same for all configurations. They are detailed in the following table.

Signal groups	Voltage reference	SODIMM pin number	Nominal voltage
UART1-UART5 CSI LCD NAND SD1 JTAG GPIO1 ENET1-ENET2	3V3_IO	155	3.3
SNVS_TAMPER[9:0]	VDD_SNVS_IN	143	3.0

What is interfaced to 3.3V signals at carrier board level may be referenced to a different voltage than 3.3V_IO. However, the difference between this voltage and 3.3V_IO must not exceed 300mV. This constraint is automatically satisfied if

• one of the following ordering codes is used: DA p l r n c 0 t s, DA p l r n c 1 t s or DA p l r n c 3 t s
• the same voltage rail is used to power AXEULite SOM and 3.3V carrier board circuitry.

Since powering is strictly related to reset signals, reading of this page is highly recommended.

Fot information about power consumption, please refer to this article.

For more information about this options, please contact DAVE's sales team at sales@dave.eu

Power Supply Unit (PSU) and recommended power-up sequence

Implementing correct power-up sequence for i.MX6UL processors is not a trivial task because several power rails are involved. AXEL ULite SOM simplifies this task by embedding all the needed circuitry. The following picture shows a simplified block diagram of PSU/voltage monitoring circuitry:

Simplified block diagram of integrated power supply unit

The PSU is composed of two main blocks:

• power management integrated circuit (PMIC NXP PF3000)
• additional circuitry that completes PMIC functionalities.

The PSU:

• generates the proper power-up sequence required by i.MX6UL processor, surrounding memories and peripherals
• synchronizes the powering up of carrier board in order to prevent back power.

Power-up sequence

The typical power-up sequence is the following:

1. (optional) PMIC_LICELL is powered by a Lithium coin cell battery
   • iMX6UL SNVS domain is powered (VDD_SNVS_IN)
2. VIN_SOM main power supply rail is powered
   • iMX6UL SNVS domain is powered (VDD_SNVS_IN)
3. CPU_PORn (active-low) is driven low
4. PMIC_PWRON signal is pulled-up (unless carrier board circuitry keeps this signal low for any reason)
5. PMIC transitions from OFF to ON state
6. PMIC initiates power-up sequence as per iMX6UL requirements
7. SOM_PGOOD signal is set ti logic '1'; this active-high signal indicates that SoM's I/O is powered. This signal can be used to manage carrier board power up sequence in order to prevent back powering (from SoM to carrier board or vice versa). Generally speaking, all the circuitry that interfaces SOM's I/O signals should be powered on when SOM_PGOOD turns to logic '1'.
8. CPU_PORn is released.

For further details, please refer to , .