Difference between revisions of "AXEL ULite SOM/AXEL ULite Hardware/Power and Reset/Power Supply Unit (PSU) and recommended power-up sequence"
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(→Power Supply Unit (PSU) and recommended power-up sequence) |
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The PSU is composed of two main blocks: | The PSU is composed of two main blocks: | ||
| − | * power management integrated circuit (PMIC | + | * power management integrated circuit (PMIC NXP PF3000) |
* additional generic power management circuitry that completes PMIC functionalities. | * additional generic power management circuitry that completes PMIC functionalities. | ||
The PSU: | The PSU: | ||
| − | * generates the proper power-up sequence required by i. | + | * generates the proper power-up sequence required by i.MX6UL processor and surrounding memories and peripherals |
| − | * synchronizes the powering up of carrier board in order to prevent back power | + | * synchronizes the powering up of carrier board in order to prevent back power. |
| − | |||
=== Power-up sequence=== | === Power-up sequence=== | ||
| Line 33: | Line 32: | ||
The typical power-up sequence is the following: | The typical power-up sequence is the following: | ||
# (optional) PMIC_LICELL is powered | # (optional) PMIC_LICELL is powered | ||
| − | # | + | # VIN_SOM main power supply rail is powered |
# CPU_PORn (active-low) is driven low | # CPU_PORn (active-low) is driven low | ||
# PMIC activates PMIC_VSNVS power output | # PMIC activates PMIC_VSNVS power output | ||
| Line 39: | Line 38: | ||
# PMIC transitions from OFF to ON state | # PMIC transitions from OFF to ON state | ||
# PMIC initiates power-up sequence needed by MX6 processor | # PMIC initiates power-up sequence needed by MX6 processor | ||
| − | # | + | # SOM_PGOOD signal is raised; this active-high signal indicates that SoM's I/O is powered. This signal can be used to manage carrier board power up sequence in order to prevent back powering (from SoM to carrier board or vice versa). For additional information, please refer to the [[Power_(AxelLite)#Note_on_BOARD_PGOOD_usage | Note]] below. |
# CPU_PORn is released. | # CPU_PORn is released. | ||
| − | ==== Note on | + | ==== Note on SOM_PGOOD usage ==== |
| − | + | SOM_PGOOD is used on carrier board to implement proper power up sequencing. Generally speaking, all the circuitry that interfaces SOM's I/O signals should be powered on when SOM_PGOOD turns to logic '1'. | |
| − | |||
[[File:Axel-lite-power-good.png]] | [[File:Axel-lite-power-good.png]] | ||
Revision as of 16:16, 14 July 2016
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Contents
Introduction[edit | edit source]
AXELULite system-on-module (SOM for short) is powered by carrier board via VIN_SOM rail.
About voltage range, three supported configurations are available. These configurations are indicated by the value of the f field of the ordering code. The generic ordering code is in the form:
DA p l r n c f t sThe field f can assume the following values:
- 0, 1: power supply voltage range 3.135 - 3.465V (that is 3V3±5%)
- 2: power supply voltage range is 3.3 - 4.5V
- please note that this range can be widened by the use of an external MOSFET; for more details please refer to technical support
- 3: power supply voltage range is 3.25 - 3.465V (that us 3.3 +5%/-1.5%).
Power Supply Unit (PSU) and recommended power-up sequence[edit | edit source]
Implementing correct power-up sequence for i.MX6UL processors is not a trivial task because several power rails are involved. AXELULite SOM simplifies this task by embedding all the needed circuitry. The following picture shows a simplified block diagram of PSU/voltage monitoring circuitry:
The PSU is composed of two main blocks:
- power management integrated circuit (PMIC NXP PF3000)
- additional generic power management circuitry that completes PMIC functionalities.
The PSU:
- generates the proper power-up sequence required by i.MX6UL processor and surrounding memories and peripherals
- synchronizes the powering up of carrier board in order to prevent back power.
Power-up sequence[edit | edit source]
The typical power-up sequence is the following:
- (optional) PMIC_LICELL is powered
- VIN_SOM main power supply rail is powered
- CPU_PORn (active-low) is driven low
- PMIC activates PMIC_VSNVS power output
- PMIC_PWRON signal is pulled-up (unless carrier board circuitry keeps this signal low for any reason)
- PMIC transitions from OFF to ON state
- PMIC initiates power-up sequence needed by MX6 processor
- SOM_PGOOD signal is raised; this active-high signal indicates that SoM's I/O is powered. This signal can be used to manage carrier board power up sequence in order to prevent back powering (from SoM to carrier board or vice versa). For additional information, please refer to the Note below.
- CPU_PORn is released.
Note on SOM_PGOOD usage[edit | edit source]
SOM_PGOOD is used on carrier board to implement proper power up sequencing. Generally speaking, all the circuitry that interfaces SOM's I/O signals should be powered on when SOM_PGOOD turns to logic '1'.
[edit | edit source]
The following list describes in detail the power rails and the power related signals. Please note that PMIC regulators ouput voltages can be changed only if explicitly allowed.
- 3.3VIN: this is external main power rail. Voltage range is 3.3V±5%
- PMIC_CELL: PMIC's coin cell supply input/output
- BOARD_PGOOD: this output signal is used to indicate when carrier board's circuitry interfacing Axel Lite's I/Os has to be powered up.
For further details, please refer to the PMIC documentation.
