AXEL ULite SOM/AXEL ULite Hardware/Power and Reset/Boot process and bootstrap configuration

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Issue Date Notes


New documentation layout


Add NOR-NAND boot option information
2021/07/15 Add DLT eFuses programmed model

Boot process and bootstrap configuration[edit | edit source]

NXP iMX6UL processor implements a very flexible boot process. This versatility comes at the price of a non trivial bootstrap configuration scheme. Typical system-on-module (SOM for short) adopter does not need to deal with such a complexity. In other words, he/she expects to manage few boot configuration issues because it is assumed that most of them are "hidden" within the SOM itself. Nevertheless, there are specific applications where the system integrator needs full control of all the bootstrap configuration options, even if the design is built upon a SOM.

These two needs - ease of use and configurability - clearly push in opposite directions. During the inception of the AXEL ULite product, specific attention has been addressed to find a viable trade off to satisfy such requirements. This effort has led to the options that are detailed in the section Options for AXEL ULite users. Reader can skip directly to this paragraph, however he/she is encouraged to read this section as well, in order to get an overview of the processor's boot process.

It is worth remembering that an exhaustive discussion of this issue is beyond the scope of this article. For more details, please refer to [1].

iMX6UL bootstrap process overview[edit | edit source]

When it comes to boot process, three factors play a major role:

  • eFUSE bits
  • GPIO settings.

Generally speaking, three main boot modes are supported. These modes are selected by BOOT_MODE signals that are latched when processor comes out of reset.

BOOT_MODE[1:0] Boot type
00 Boot from eFUSEs
01 Serial downloader
10 Internal boot
11 reserved

It is worth remembering that, no matter what modes is selected, when processor reset is released, internal Boot ROM is executed. Its behavior depends on selected mode as described in the following sections.

Boot from eFUSEs[edit | edit source]

The term eFUSEs refers to an one-time-programmable (OTP) memory integrated in iMX6UL processor. This memory is organized in several 32-bit words. Some of these words - named BOOT_CFG - are used to store configuration bits that affect the boot process, when Boot from eFUSEs mode is selected. In this case, Boot ROM reads BOOT_CFG words and acts consequently. In particular it tries to retrieve the Program Image [1] from the selected device (NOR flash, NAND flash, SD card etc.), as per BOOT_CFG bits.

BOOT_CFG includes many configuration settings. Some of them are particularly important for the boot strategy:

  • BT_FUSE_SEL (shipped value = 0)
  • SDMMC_MFG_DISABLE (shipped value = 0)

The use of these settings will be more clear soon.

In case Program Image retrieval fails, Boot ROM can attempt to retrieve an alternative valid Program Image. For more details please refer to [1].

[1] Program Image includes - but it is not limited to - the code that is executed by the processor when Boot ROM jumps to it.

Internal boot[edit | edit source]

This mode is similar to Boot from eFUSEs with one notable difference related to the so called GPIO override option.

The selection of the device from which the Boot ROM retrieves Program Image along with several further device-specific configuration settings, can be done in two different ways, depending on BT_FUSE_SEL bit:

  • 0 (shipped value): GPIOs
    • This technique - also known as GPIO override - is typically used during the development stage. It allows to use 24 GPIOs (specifically LCD1_DATA[23:00]) to configure BOOT_CFG bits.
  • 1: eFUSE.
    • In this case BOOT_CFG bits are fetched from OTP memory.

Serial downloader[edit | edit source]

Serial Downloader mode is used to download a Program Image over one of the following connections:

  • USB OTG1
  • UART1
  • UART2.

When this mode is selected, Boot ROM continuously polls for a connection over these interfaces.

It is worth remembering that, when Serial Downloader is enabled, Boot ROM needs to initialize muxing of UART1/UART2 signals as per the following table.

Ball name Ball reference Signal name Mux mode
UART1_TX_DATA K14 uart1.TX_DATA Alt 0
UART1_RX_DATA K16 uart1.RX_DATA Alt 0
UART2_TX_DATA J17 uart2.TX_DATA Alt 0
UART2_RX_DATA J16 uart2.RX_DATA Alt 0

Since these pads may be used to implement different functions other than UART signals in customer's application, system integrator needs to verify that the Serial Downloader - if used - is electrically compatible with his/her own carrier board.

Typical scenario[edit | edit source]

This section describes the typical scenario related to the development/manufacturing process of an iMX6UL-based system.

During the development stage, processor is configured as follows:

  • Boot mode is Internal boot, selected via BOOT_MODE pins
  • eFUSE have not been programmed, thus GPIO override is enabled because BT_FUSE_SEL is 0
  • according to GPIOs settings, Boot ROM retrieves program image from the selected device
  • LCD1_DATA[23:00] are connected to a circuitry [1] that allows to change easily GPIO settings in order to test different configurations.

Once the product has been validated and the production boot strategy has been defined, the definitive boot configuration needs to be stored permanently in OTP memory. This operation is usually performed during the manufacturing process. To implement it, the Manufacture mode may come to help. This mode is associated to the SDMMC_MFG_DISABLE setting that by default is 0 (manufacture mode enabled). Therefore the typical manufacturing process looks like this:

  • BOOT_MODE pins are set to 00 in order to select Boot from eFUSEs boot mode
  • at the first power up
    • if SD/MMC card connected to SDHC1 is found [2], Boot ROM tries to load a Program Image from it, as SDMMC_MFG_DISABLE is 0
    • if no card is found, Boot ROM switches to serial download mode
      • as a consequence, Boot ROM polls for a connection over these interfaces: USB OTG1, UART1 and UART2
    • Boot ROM jumps to user code (no matter if this has been retrieved from SD/MMC card or downloaded through serial connection)
    • user code takes care of several tasks including the programming of eFUSEs; in particular:
      • SDMMC_MFG_DISABLE is blown [3] in order to disable permanently manufacture mode
      • BT_FUSE_SEL is blown in order to indicate to Boot ROM that eFUSEs have been programmed
      • FORCE_INTERNAL_BOOT is blown in order to ignore BOOT_MODE pins from now on
      • depending of application's security requirements, other eFUSEs may be blown; for example SDP_DISABLE is blown in case serial download has to be completely disabled
  • the system has been fully programmed and can be finally booted in its production configuration
    • as FORCE_INTERNAL_BOOT has been blown, Internal boot mode is selected, no matter the status of BOOT_MODE pin is
    • as BT_FUSE_SEL is 1, Boot ROM retrieves the Program Image according to BOOT_CFG bits that are read from eFUSEs
    • Boot ROM jumps to user code and normal boot process is performed (this typically consists of the execution of the bootloader U-Boot and then the operating system kernel).

[1] This circuitry - that will not be populated in mass production stage - operates until Boot ROM reads GPIO pads status. Once this operation is completed, GPIO pads should be electrically disconnected from this circuitry in order to prevent any interference with the functional use of these signals.

[2] The detection of SD/MMC card presence is done by polling the status of the pad SD1_CD. If it is 0, SD/MMC card is present.

[3] It means it is set to 1.

AXEL ULite boot options[edit | edit source]

From the point of view of boot configuration programming, AXEL ULite portfolio consists of two basic categories of ordering codes:

  1. part numbers in the form DLTx0xx00x2R have eFUSEs not programmed
  2. the other ordering codes have eFUSE programmed as detailed in the following section.

For convenience, the products belonging to the first category will be denoted as NP-eFUSE. The others will be referred as P-eFUSE.

P-eFUSE ordering codes[edit | edit source]

P-EFUSE codes address users that don't need full control of boot configuration and can use one of the preconfigured options. These configurations are intended to satisfy most commonly used boot schemes. Nevertheless, users are strongly recommended to understand the limitations of such configurations in order to verify they meet system requirements.

Generally speaking, AXEL ULite supports two kind of memories as internal boot devices: NOR flash (connected to ESCPI1 interface) and NAND flash.

These devices can be combined differently. However, no matter how NAND and NOR flash are combined, all of P-eFUSE ordering codes have:

  • SDMMC_MFG_DISABLE set to 0: manufacture mode is enabled
  • BT_FUSE_SEL is set to 1, meaning that that eFUSEs have been programmed
  • FORCE_INTERNAL_BOOT is set to 0, in order to let BOOT_MODE pins to select main boot mode
  • SEC_CONFIG[1:0] are set to 01 to allow any program image, even if authentication fails (this option is intended for non-secure products)
  • eFuse 0x470[4] is set to 1, to disable UART serial download.

This leads to three different boot flows and that are shown in the following pictures.

NAND-NOR option[edit | edit source]

This configuration makes use of NAND flash as primary internal boot device. NOR flash is used as secondary boot device where, for example, a so-called golden image of the bootlader can be stored.

Boot flow for ordering code in the form DLTxxxx20x2R

NAND-only option[edit | edit source]

This configuration makes use of NAND flash as primary - and only - internal boot device.

Boot flow for ordering code in the form DLTx0xx20x2R

NOR-NAND option[edit | edit source]

This configuration makes use of NOR flash as primary internal boot device. Nevertheless, NAND flash is available for generic storage. NAND flash can not be used as booting device.

Boot flow for ordering code in the form DLTxxxx10x2R
  • NOR option: From the point of view of boot process, this configuration is identical to the NOR-NAND option. This is clearly cheaper because NAND flash is not populated.

The following table details eFUSE programming of available P-eFUSE ordering codes.

TBD.png Section not completed yet

P-eFUSE products yet provides a moderated freedom in terms of configurability and openness. Generally speaking, this may affect system security. Hence it is strongly recommended that system integrator does a detailed assessment in case he/she is considering the use of P-eFUSE SOMs, especially if security concerns are relevant.

NP-eFUSE ordering codes[edit | edit source]

Users who need to have the full control of the boot process should choose one of the NP-eFUSE part numbers. This allows them to be able to

  • program eFUSEs by themselves
  • implement circuitry at carrier board level to exploit GPIO override
  • decide to use GPIO override approach even for mass production.
AXEL ULite adapter[edit | edit source]

To ease the development effort of the customers working with NP-eFUSE SOMs, DAVE Embedded Systems has made available a specific adapter board. For more information please see this page.

References[edit | edit source]


  1. 1.0 1.1 NXP, IMX6ULRM, i.MX 6UltraLite Applications Processor Reference Manual