Changes

NXP iMX6UL processor implements a very flexible boot process. This versatility comes at the price of a non trivial bootstrap configuration scheme. Typical system-on-module (SOM for short) adopter does not want/need to deal with such a complexity. In other words , he/she expects to manage few boot configuration issues because it is assumed they that most of them are handled by "hidden" within the SOM itself. Nevertheless, there are specific applications where the system integrator needs full control of all the bootstrap configuration options, even if the design is built upon a SOM.

These two needs - ease of use and configurability - clearly push in opposite directions. During the conception inception of the AXEL ULite product AXELULite, specific attention has been addressed to find a viable trade off to satisfy such requirements. This effort has led to the options that are detailed in the section [[#Options for AXELULite AXEL ULite users|Options for AXELULite AXEL ULite users]]. Before skipping Reader can skip directly to itthis paragraph, it however he/she is recommended encouraged to read [[#Overview of NXP iMX6UL bootstrap process|this section]] that depicts as well, in order to get an overview of the processor's boot process.  It is worth remembering that an exhaustive discussion of this issue is beyond the scope of this article. For more details about it , please refer to <ref name="IMX6ULRM">NXP , IMX6ULRM, ''i.MX 6UltraLite Applications Processor Reference Manual''</ref>.

*<code>BT_FUSE_SEL </code> (shipped value = 0)*<code>SDMMC_MFG_DISABLE </code> (shipped value = 0)*<code>FORCE_INTERNAL_BOOT</code>.

| UART1_TX_DATA||TBDK14||uart1.TX_DATA||Alt 0

| UART1_RX_DATA||TBDK16||uart1.RX_DATA||Alt 0

| UART2_TX_DATA||TBDJ17||uart2.TX_DATA||Alt 0

| UART2_RX_DATA||TBDJ16||uart2.RX_DATA||Alt 0

*according to GPIOs settings, Boot ROM retrieves program image from the selected device.

Once the product has been qualified validated and the production boot strategy has been defined, the definitive boot configuration needs to be stored permanently in OTP memory. This operation is usually performed during the manufacturing process. To implement it, the ''Manufacture mode'' may come to help. This mode is associated to the <code>SDMMC_MFG_DISABLE</code> setting that by default is 0 (manufacture mode enabled). Therefore the typical manufacturing process looks like this:

**if SD/MMC card connected to SDHC1 is found [2], Boot ROM tries to load a Program Image from SDHC1 because it, as <code>SDMMC_MFG_DISABLE</code> is 0**if no SD/MMC card is found [2], Boot ROM switches to serial download mode

***<code>BT_FUSE_SEL</code> is blown in order to indicarte indicate to Boot ROM that eFUSEs have been programmed***<code>FORCE_INTERNAL_BOOT</code> is blown in order to ignore <code>BOOT_MODE </code> pins from now on

[1] This circuitry - that will not be populated in mass production stage - is such that it operates until Boot ROM reads GPIO pads status. Once this operation is completed, GPIO pads should be electrically disconnected from this circuitry in order to prevent any interference with the actual functional use of these signals.

==Options for AXEL ULite users==From the point of view of boot configuration programming, AXEL ULite portfolio consists of two basic categories of ordering codes:#part numbers in the form TBD have eFUSEs not programmed#the other ordering codes have eFUSE programmed as detailed in the [[#P-eFUSE ordering codes|following section]].For convenience, the products belonging to the first category will be denoted as ''NP-eFUSE''. The others will be referred as ''P-eFUSE''. ===P-eFUSE ordering codes===P-EFUSE codes address users that don't need full control of boot configuration and can use one of the preconfigured options. These configurations are intended to satisfy most commonly used boot schemes. Nevertheless, '''users are strongly recommended to understand the limitations of such configurations in order to verify they meet system requirements'''. Generally speaking, AXEL ULite supports two kind of memories as internal boot devices: NOR flash (connected to ESCPI1 interface) and NAND flash.  These devices can be combined differently. However, no matter how NAND and NOR flash are combined, all of P-eFUSE ordering codes have:*<code>SDMMC_MFG_DISABLE</code> set to 0: ''manufacture mode'' is '''enabled'''*<code>BT_FUSE_SEL</code> is set to 1, meaning that that eFUSEs have been programmed*<code>FORCE_INTERNAL_BOOT</code> is set to 0, in order to let <code>BOOT_MODE</code> pins to select main boot mode*<code>SEC_CONFIG[1:0]</code> are set to 01 to allow any program image, even if authentication fails ('''this option is intended for non-secure products''')*<code>eFuse 0x470[4]</code> is set to 1, to disable UART serial download.This leads to three different boot flows and that are shown in the following pictures. '''NAND-NOR option''' This configuration makes use of NAND flash as primary internal boot device. NOR flash is used as secondary boot device where, for example, a so-called ''golden image'' of the bootlader can be stored. [[File:AXELULite users-boot-NAND-NOR.png|thumb|center|750px|Boot flow for ordering code in the form TBD]]  '''NAND-only option''' This configuration makes use of NAND flash as primary - and only - internal boot device. [[File:AXELULite-boot-NAND.png|thumb|center|750px|Boot flow for ordering code in the form TBD]]  '''NOR-NAND option''' This configuration makes use of NOR flash as primary internal boot device. Nevertheless, NAND flash is available for generic storage. NAND flash can not be used as booting device.[[File:AXELULite-boot-NOR-NAND.png|thumb|center|750px|Boot flow for ordering code in the form TBD]] *NOR option: From the point of view of boot process, this configuration is identical to the NOR-NAND option. This is clearly cheaper because NAND flash is not populated.   The following table details eFUSE programming of available P-eFUSE ordering codes.{|class="wikitable" style="text-align: center;"|-!p/n!BOOT_CFG1!BOOT_CFG2!BOOT_CFG4!Note|-| TBD||TBD||TBD||TBD||TBD|-| TBD||TBD||TBD||TBD||TBD|-| TBD||TBD||TBD||TBD||TBD|-| TBD||TBD||TBD||TBD||TBD|} P-eFUSE products yet provides a moderated freedom in terms of configurability and openness. Generally speaking, this may affect system security. '''Hence it is strongly recommended that system integrator does a detailed assessment in case he/she is considering the use of P-eFUSE SOMs, especially if security concerns are relevant'''. ===NP-eFUSE ordering codes===Users who need to have the '''full control''' of the boot process should choose one of the NP-eFUSE part numbers. This allows them to be able to*program eFUSEs by themselves*implement circuitry at carrier board level to exploit ''GPIO override''*decide to use ''GPIO override'' approach even for mass production. ====AXEL ULite adapter====To ease the development effort of the customers working with NP-eFUSE SOMs, DAVE Embedded Systems has made available a specific adapter board. For more information please see [[AXEL ULite adapter|this page]].