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<section begin="History" />
{| style="border-collapse:collapse; "
!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History
|-
|-
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|X.Y.Z{{oldid|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"14315|Month Year2020/12/23}}|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|TBDNew documentation layout
|-
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |{{oldid|16736|2022/06/30}}
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Update Order code table
|-
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fbededed; padding:5px; color:#000000"|[TBD_link X.Y.Z]|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"{{oldid|Month Year|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|TBD|-|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|...|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"17009|...2020/07/22}}|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fbededed; padding:5px; color:#000000"|...Update Order code table
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |2023/05/04
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |minor change on boot configurations
|}
<section end="History" />__FORCETOC__<section begin="Body" /> ''TBD: sostituire la codifica con quella del prodotto''
==Part number composition==
AXEL Lite SOM module part number is identified by the following digit-code table:
{| class="wikitable" style="width:50%"
! style="width:10%" |Part number structure
! style="width:40%" |Options
! style="width:20%" |Description
|-
!Family
| '''DXL'''
| Family prefix code
|-
!SOC
|
* A: i.MX6Solo 800MHz -40/125°C
* B: i.MX6Solo 1GHz 0/95°C
* C: i.MX6 DualLite 1GHz 0/95°C
* E: i.MX6 Quad 800MHz -40/105°C
* F: i.MX6 DualPlus 800MHz -40/105°C
* H: i.MX6 Quad 1GHz -40/105°C
* I: i.MX6 Quad 1.2GHz -20/105°C
* M: i.MX6 DualLite 800MHz -40/105°C
|System On Chip definition
|-
!NOR SPI
|
* 0: 0MB
* 4: 16MB
* 5: 32MB
* 6: 64MB
|Flash memory NOR size
|-
!RAM
|
* 1: 1GB
* 2: 2GB
* 9: 512MB
|DDR memory RAM size
|-
!NAND
|
* 0: 0MB
* 1: 1GB NAND SLC
* 2: 2GB NAND SLC
* 4: 4GB NAND MLC
* 7: 128MB NAND SLC
* 8: 256MB NAND SLC
* 9: 512MB NAND SLC
|Flash memory NAND size
|-
!Boot/bus width
|
* 0: SPI NOR/SD1 - 64bit
* 1: NAND/SD - 32bit
* 2: SPI NOR/SD - 32 bit
* 3: NAND/SD - 64 bit
* 4: NAND/SD - 64 bit NO CAN
* 6: eMMC/SD3 - 64 bit
* 7: eMMC/SD3 - 64 bit - NO CAN
|Boot options and RAM Bus width
|-
!Temperature range
|
* C - Commercial
* I - Industrial
|For the DAVE Embedded Systems' product Temperature Range classification, please find more information at the page [[Products Classification]]
|-
!PCB revision
|
* 0: first version
* 1: revision A
* 2: revision B
* 3: revision C
|PCB release may change for manufacturing purposes (i.e. text fixture adaptation)
|-
!Manufacturing option
|R: RoHS
|typically connected to production process and quality
|-
!Software Configuration
|
* -00: standard factory u-boot pre-programmed
|If customers require custom SW deployed this section should be defined and agreed
|}
=== Example ===
AXEL Lite SOM code '''DXLM0213C3R-00'''
* DXL part number prefix- AXEL Lite SOM module* SOC:** A: i.MX6Solo 800MHz M -40/125°C** B: i.MX6Solo 1GHz 0/95°C** C: i.MX6 DualLite 1GHz 0/95°C** E: i.MX6 Quad 800MHz -40/105°C** F: i.MX6 DualPlus 800MHz -40/105°C** H: i.MX6 Quad 1.2GMHz -40/105°C** I: i.MX6 Quad 1.2GMHz -20/105°C** M: i.MX6 DualLite 800MHz 0 -40/105°C* NO NOR SPI:onboard** 0: 0MB** 4: 16MB** 5: 32MB** 6: 64MB* RAM:** 1: 1GB** 2: - 2GBDDR3 ** 9: 512MB* NAND:** 0: 0MB** 1: - 1GB NAND SLC** 2: 2GB NAND SLC** 4: 4GB NAND MLC ** 7: 128MB NAND SLC** 8: 256MB NAND SLC** 9: 512MB NAND SLC* Boot:** 0: SPI NOR - 64bit** 1: NAND/SD - 32bit** 2: SPI NOR - 32 bit** 3: NAND/SD - 64 bit** 4: boot from NAND/SD - 32 bit** 6: eMMC/SD3 - wuth 64 bitbus width* Temperature range** C - Commercialtamperature range (i.e. 0/95°C)** I 3 - Industrial* PCB revision** 0: first version** 1: revision A** 2: revision B** 3: revision C* Manufacturing option** R: - RoHSmanufacturing process* Software Configuration** -00: standard factory u-boot pre-programmed
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[[Category:AXEL Lite]]