Bureaucrats, dave_user, Administrators
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<section begin="History" />
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== System boot ==
* once it is satisfied, it executes the boot code
=== Boot options ===
Two options are available related to system boot. They are identified by the ''Boot field '' of the ordering code as follows:* Boot field = 0 (SOM code: DXLxxxx'''0'''xxR): "SPI NOR / SD " option * Boot field = 1 (SOM code: DXLxxxx0xxRDXLxxxx'''1'''xxR)* 1: "NAND / SD " option (SOM code: DXLxxxx1xxR)For both options , the selection of the primary boot device is determined by the [[AXEL Lite SOM/AXEL Lite Hardware/Power and Reset/Reset scheme and control signals|BOOT_MODE_SEL ]] signal as described in the following sections. BOOT_MODE_SEL is latched when processor reset is released.
In any case, boot process is managed by on-chip boot ROM code that is described in detail in processor's Reference Manual.
==== SPI NOR / SD option ====
Selection of primary boot device is determined by the BOOT_MODE_SEL signal as follows:
* BOOT_MODE_SEL = 0
** in case no valid image is found in NOR flash, boot ROM shall enable USB serial download mode automatically
==== NAND / SD option ====
Selection of primary boot device is determined by the BOOT_MODE_SEL signal as follows:
* BOOT_MODE_SEL = 0
===Important note for DualLite/Solo based products (''manufacture mode'' management)===
When Dual Lite or Solo processor are used, GPIO_1 and GPIO_4 signals need to be kept high during bootstrap stage in order to prevent the intervention of bootrom's ''manufacture mode''. Bootstrap stage has to be intended as the time elapsing between the release of hardware reset (CPU_PORn) and the execution of the first instruction of user code (typically this is the reset vector of U-Boot boot loader). Please note that, in case GPIO_1 signal is used to implement [[Reset_scheme_(AxelLite)AXEL_Lite_SOM/AXEL_Lite_Hardware/Power_and_Reset/Reset_scheme_and_control_signals#Handling_CPU-initiated_software_reset|software reset circuit]], it is high during bootstrap stage by design.
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[[Category:AXEL Lite]]