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Created page with "{{subst:System_boot | nome-som=AXEL Lite | kit-code=MX6}}"
<section begin=History/>
{| style="border-collapse:collapse; "
!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History
|-
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Version
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes
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|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|X.Y.Z
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Month Year
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|TBD
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|-
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|[TBD_link X.Y.Z]
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Month Year
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|TBD
|-
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|...
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|...
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|...
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|}
<section end=History/>
<section begin=Body/>
== System boot ==
The boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM core to begin execution starting from the on-chip boot ROM. The boot ROM:
* determines whether the boot is secure or non-secure
* performs some initialization of the system and clean-ups
* reads the mode pins to determine the primary boot device
* once it is satisfied, it executes the boot code
''TBD: le sezioni di seguito sono valide - come esempio per AXEL Lite - da rivedere per gli altri prodotti ''
== Boot options ==
Two options are available related to system boot. They are identified by the Boot field of the ordering code as follows:
* 0: SPI NOR / SD option (SOM code: DXLxxxx0xxR)
* 1: NAND / SD option (SOM code: DXLxxxx1xxR)
For both options the selection of primary boot device is determined by the BOOT_MODE_SEL signal as described in the following sections. BOOT_MODE_SEL is latched when processor reset is released.
In any case, boot process is managed by on-chip boot ROM code that is described in detail in processor's Reference Manual.
=== SPI NOR / SD option ===
Selection of primary boot device is determined by the BOOT_MODE_SEL signal as follows:
* BOOT_MODE_SEL = 0
** primary boot device is SD1
* boot ROM will try to boot a valid image from the SD card first, and then from the SPI NOR. In case no valid image is found, boot ROM shall enable USB serial download mode automatically
* BOOT_MODE_SEL = 1 or floating
** primary boot device is SPI NOR flash connected to eCSPI1
** in case no valid image is found in NOR flash, boot ROM shall enable USB serial download mode automatically
=== NAND / SD option ===
Selection of primary boot device is determined by the BOOT_MODE_SEL signal as follows:
* BOOT_MODE_SEL = 0
** primary boot device is SD1
** in case no valid image is found in SD card, boot ROM shall enable USB serial download mode automatically
* BOOT_MODE_SEL = 1 or floating
** primary boot device is NAND flash
** in case no valid image is found in NAND flash, boot ROM shall enable USB serial download mode automatically
===Important note for DualLite/Solo based products (''manufacture mode'' management)===
When Dual Lite or Solo processor are used, GPIO_1 and GPIO_4 signals need to be kept high during bootstrap stage in order to prevent the intervention of bootrom's ''manufacture mode''. Bootstrap stage has to be intended as the time elapsing between the release of hardware reset (CPU_PORn) and the execution of the first instruction of user code (typically this is the reset vector of U-Boot boot loader). Please note that, in case GPIO_1 signal is used to implement [[Reset_scheme_(AxelLite)#Handling_CPU-initiated_software_reset|software reset circuit]], it is high during bootstrap stage by design.
----
[[Category:AXEL Lite]]
{| style="border-collapse:collapse; "
!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History
|-
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Version
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes
|-
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|X.Y.Z
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Month Year
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|TBD
|-
|-
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|[TBD_link X.Y.Z]
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Month Year
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|TBD
|-
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|...
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|...
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|...
|-
|}
<section end=History/>
<section begin=Body/>
== System boot ==
The boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM core to begin execution starting from the on-chip boot ROM. The boot ROM:
* determines whether the boot is secure or non-secure
* performs some initialization of the system and clean-ups
* reads the mode pins to determine the primary boot device
* once it is satisfied, it executes the boot code
''TBD: le sezioni di seguito sono valide - come esempio per AXEL Lite - da rivedere per gli altri prodotti ''
== Boot options ==
Two options are available related to system boot. They are identified by the Boot field of the ordering code as follows:
* 0: SPI NOR / SD option (SOM code: DXLxxxx0xxR)
* 1: NAND / SD option (SOM code: DXLxxxx1xxR)
For both options the selection of primary boot device is determined by the BOOT_MODE_SEL signal as described in the following sections. BOOT_MODE_SEL is latched when processor reset is released.
In any case, boot process is managed by on-chip boot ROM code that is described in detail in processor's Reference Manual.
=== SPI NOR / SD option ===
Selection of primary boot device is determined by the BOOT_MODE_SEL signal as follows:
* BOOT_MODE_SEL = 0
** primary boot device is SD1
* boot ROM will try to boot a valid image from the SD card first, and then from the SPI NOR. In case no valid image is found, boot ROM shall enable USB serial download mode automatically
* BOOT_MODE_SEL = 1 or floating
** primary boot device is SPI NOR flash connected to eCSPI1
** in case no valid image is found in NOR flash, boot ROM shall enable USB serial download mode automatically
=== NAND / SD option ===
Selection of primary boot device is determined by the BOOT_MODE_SEL signal as follows:
* BOOT_MODE_SEL = 0
** primary boot device is SD1
** in case no valid image is found in SD card, boot ROM shall enable USB serial download mode automatically
* BOOT_MODE_SEL = 1 or floating
** primary boot device is NAND flash
** in case no valid image is found in NAND flash, boot ROM shall enable USB serial download mode automatically
===Important note for DualLite/Solo based products (''manufacture mode'' management)===
When Dual Lite or Solo processor are used, GPIO_1 and GPIO_4 signals need to be kept high during bootstrap stage in order to prevent the intervention of bootrom's ''manufacture mode''. Bootstrap stage has to be intended as the time elapsing between the release of hardware reset (CPU_PORn) and the execution of the first instruction of user code (typically this is the reset vector of U-Boot boot loader). Please note that, in case GPIO_1 signal is used to implement [[Reset_scheme_(AxelLite)#Handling_CPU-initiated_software_reset|software reset circuit]], it is high during bootstrap stage by design.
----
[[Category:AXEL Lite]]