Difference between revisions of "AXEL Lite SOM/AXEL Lite Hardware/Peripherals/SPI"
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=== Description === | === Description === | ||
| − | The SPI interface available on AXEL Lite is based on i.MX6 | + | The SPI interface available on AXEL Lite is based on i.MX6 ECSPI blocks. |
The ECSPI port supports the following standards and features: | The ECSPI port supports the following standards and features: | ||
Revision as of 13:38, 31 August 2022
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Peripheral SPI[edit | edit source]
The Enhanced Configurable Serial Peripheral Interface (ECSPI) is a full-duplex, synchronous, four-wire serial communication block.
Description[edit | edit source]
The SPI interface available on AXEL Lite is based on i.MX6 ECSPI blocks.
The ECSPI port supports the following standards and features:
- Full-duplex synchronous serial interface
- Master/Slave configurable
- Four Chip Select (SS) signals to support multiple peripherals
- Transfer continuation function allows unlimited length data transfers
- 32-bit wide by 64-entry FIFO for both transmit and receive data
- Polarity and phase of the Chip Select (SS) and SPI Clock (SCLK) are configurable
- Direct Memory Access (DMA) support
- Max operation frequency up to the reference clock frequency
Pin mapping[edit | edit source]
The Pin mapping is described in the Pinout table section
