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__FORCETOC__

==Peripheral MIPI ==

~~''TBD: sostituire le sezioni con le informazioni sull'uso della periferica''~~The CSI-2 Host Controller is a digital core that implements all protocol functions defined in the MIPI CSI-2 Specification, providing an interface between the System and the MIPI~~''Nell'esempio di seguito c'è la descrizione dell'interfaccia HDMI''~~D-PHY, allowing the communication with a MIPI CSI-2 compliant Camera Sensor

=== Description ===

The MIPI interface available on AXEL Lite is based on i.MX6 SoCand support the following features:* Compliant with MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2), Version 1. 00 - 29 November 2005* Interface with MIPI D-PHY following PHY Protocol Interface (PPI), as defined in MIPI Alliance Specification for D-PHY, Version 1.00.00 - 14 May 2009* Supports up to 2 (S/DL) and 4 (D/Q) D-PHY Rx Data Lanes* Dynamically configurable multi-lane merging* Long and Short packet decoding* Timing accurate signaling of Frame and Line synchronization packets* Support for several frame formats such as:** General Frame or Digital Interlaced Video with or without accurate sync timing** Data type (Packet or Frame level) and Virtual Channel interleaving* 32-bit Image Data Interface delivering data formatted as recommended in CSI-2 Specification* Supports all primary and secondary data formats:** RGB, YUV and RAW color space definitions** From 24-bit down to 6-bit per pixel** Generic or user-defined byte-based data types* Error detection and correction: PHY, Packet, Line, Frame

=== Camera ports ===

U0007

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