Difference between revisions of "AXEL Lite SOM/AXEL Lite Hardware/Peripherals/LVDS"
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==Peripheral LVDS == | ==Peripheral LVDS == | ||
| − | + | The LVDS Display Bridge (LDB) connects the IPU (Image Processing Unit) to an External LVDS Display Interface. | |
| − | + | ||
| + | The purpose of the LDB is to support flow of synchronous RGB data from the IPU to external display devices through the LVDS interface. | ||
| + | |||
| + | This support covers all aspects of these activities: | ||
| + | * Connectivity to relevant devices - Displays with LVDS receivers | ||
| + | * Arranging the data as required by the external display receiver and by LVDS display standards | ||
| + | * Synchronization and control capabilities | ||
=== Description === | === Description === | ||
| − | The LVDS interface available on AXEL Lite is based on | + | The LVDS interface available on AXEL Lite is based on i.MX6 SoC and provides two LVDS interfaces. |
| − | The LVDS | + | The LVDS ports may be used as follows: |
| + | * Single channel output | ||
| + | * Dual channel output (one input source, two channels outputs for two displays) | ||
| + | * Split channel output (one input source, splitted to 2 channels on output) | ||
| + | * Separate 2 channel output (2 input sources from IPU) | ||
| − | + | The output LVDS port complies to the EIA-644-A standard. | |
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===Pin mapping=== | ===Pin mapping=== | ||
Revision as of 10:57, 18 September 2020
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Peripheral LVDS[edit | edit source]
The LVDS Display Bridge (LDB) connects the IPU (Image Processing Unit) to an External LVDS Display Interface.
The purpose of the LDB is to support flow of synchronous RGB data from the IPU to external display devices through the LVDS interface.
This support covers all aspects of these activities:
- Connectivity to relevant devices - Displays with LVDS receivers
- Arranging the data as required by the external display receiver and by LVDS display standards
- Synchronization and control capabilities
Description[edit | edit source]
The LVDS interface available on AXEL Lite is based on i.MX6 SoC and provides two LVDS interfaces.
The LVDS ports may be used as follows:
- Single channel output
- Dual channel output (one input source, two channels outputs for two displays)
- Split channel output (one input source, splitted to 2 channels on output)
- Separate 2 channel output (2 input sources from IPU)
The output LVDS port complies to the EIA-644-A standard.
Pin mapping[edit | edit source]
The Pin mapping is described in the Pinout table section
