Difference between revisions of "AXEL Lite SOM/AXEL Lite Hardware/Peripherals/GPIO"
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| − | |style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"| | + | |style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|New documentation layout |
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<section end=History/> | <section end=History/> | ||
| + | __FORCETOC__ | ||
<section begin=Body/> | <section begin=Body/> | ||
| − | ==Peripheral | + | ==Peripheral GPIO == |
| − | + | The GPIO general-purpose input/output peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs. | |
| − | |||
=== Description === | === Description === | ||
| − | The GPIOs interface available on AXEL Lite is based on | + | The GPIOs interface available on AXEL Lite is based on i.MX6 SoC. |
| − | The | + | The GPIO functionality is provided through registers, an edge-detect circuit, and interrupt generation logic. |
| − | + | When configured as an output, it is possible to write to an internal register to control the state driven on the output pin. When configured as an input, it is possible to detect the | |
| − | + | state of the input by reading the state of an internal register. In addition, the GPIO peripheral can produce CORE interrupts. | |
| − | |||
| − | |||
===Pin mapping=== | ===Pin mapping=== | ||
Revision as of 09:28, 27 October 2020
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| Version | Issue Date | Notes | |
| 1.0.0 | Oct 2020 | New documentation layout | |
Peripheral GPIO[edit | edit source]
The GPIO general-purpose input/output peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs.
Description[edit | edit source]
The GPIOs interface available on AXEL Lite is based on i.MX6 SoC.
The GPIO functionality is provided through registers, an edge-detect circuit, and interrupt generation logic.
When configured as an output, it is possible to write to an internal register to control the state driven on the output pin. When configured as an input, it is possible to detect the state of the input by reading the state of an internal register. In addition, the GPIO peripheral can produce CORE interrupts.
Pin mapping[edit | edit source]
The Pin mapping is described in the Pinout table section
