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<section begin=History/>
{| style="border-collapse:collapse; "
!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History
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!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Version!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes
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|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|1.0.0|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Sep 2020/10/23|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|New documentation layout documentation
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{| class="wikitable" |
| align="center" style="background:#f0f0f0;"|'''Processor'''| align="center" style="background:#f0f0f0;"|'''# Cores'''| align="center" style="background:#f0f0f0;"|'''Clock'''| align="center" style="background:#f0f0f0;"|'''L2 Cache'''| align="center" style="background:#f0f0f0;"|'''DDR3'''| align="center" style="background:#f0f0f0;"|'''Graphics Acceleration'''| align="center" style="background:#f0f0f0;"|'''IPU'''| align="center" style="background:#f0f0f0;"|'''VPU'''| align="center" style="background:#f0f0f0;"|'''SATA-II'''
|-
| i.MX6 Solo || 1 ||800 MHz<br>1 GHz ||512 KB ||32 bit @ 400 MHz ||3D: Vivante GC880<br>2D: Vivante GC320<br>Vector: N.A. ||1x ||1x ||N.ANo|-|i.MX6 DualLite|2|850 MHz<br>1 GHz|512 KB|64 bit @ 533 MHz|3D: Vivante GC880<br>2D: Vivante GC320|1x|1x|No
|-
| i.MX6 Dual || 2 ||850 MHz<br>1 GHz<br>1.2 GHz ||1 MB ||64 bit @ 533 MHz ||3D: Vivante GC2000<br>2D: Vivante GC320<br>Vector: Vivante GC335 ||2x ||2x || Yes
=== NOR flash bank ===
NOR flash is a Serial Peripheral Interface (SPI) device. This device is connected to the eCSPI channel 5 1 and by default it acts as boot memory. The following table reports the NOR flash specifications:
{| class="wikitable" |
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| '''CPU connection'''||eCSPI channel 51
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| '''Size min'''||8 MB
| '''Size max'''||64 MB
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| '''Chip select'''||ECSPI5_SS0ECSPI1_SS0
|-
| '''Bootable'''||Yes
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