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!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History
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!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes
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|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|1.0.02021/09/22|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Oct 2020New documentation layout|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|First DESK release
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<section end=History/>
__FORCETOC__
<section begin=Body/>
==LVDS ==
* J8 is a Hirose (cod. DF13A-20DP-1.25V) double row 1.25mm pitch miniature crimping connector
* J9 is a Hirose (cod. DF13A-20DP-1.25V) double row 1.25mm pitch miniature crimping connector
[[File:AXEL Lite-EVB-LVDS-connector.png|thumb|center| 500px|LVDS connectors]]
===Signals ===
! latexfontsize="scriptsize"| SOM Pin#
! latexfontsize="scriptsize"| Pin name
! latexfontsize="scriptsize"| RS-232Pin function! latexfontsize="scriptsize"| RSPin Notes|-| 1, 2 || - || 3.3V_LCD0 || 3.3 V|| |-| 3, 4, 7, 10, 13, 16, 19 | - || DGND || Ground|| |-| 5 || J10.159 || LVDS1_TX0_N || LVDS Data 0 -|| |-| 6 || J10.161 || LVDS1_TX0_P || LVDS Data 0 +|| |-| 8 || J10.163 || LVDS1_TX1_N || LVDS Data 1 -|| |-| 9 || J10.165 || LVDS1_TX1_P || LVDS Data 1 +|| |-| 11 || J10.167 || LVDS1_TX2_N || LVDS Data 2 -|| |-| 12 || J10.169 || LVDS1_TX2_P || LVDS Data 2 +|| |-422! latexfontsize="scriptsize"| RS14 || J10.155 || LVDS1_CLK_N || LVDS Clock -|| |-| 15 || J10.157 || LVDS1_CLK_P || LVDS Clock +|| |-| 17 || J10.171 || LVDS1_P17 || Mount options|| LVDS1_TX3_N option |-485| 18 || J10.173 || LVDS1_P18 || Mount options|| LVDS1_TX3_P option
|-
| 20 || J10.46 || LVDS1_P20 || Mount options|| GND or PWM (J10.46) option
|}
=== Device mapping ===
* LVDS0 is mapped to <code>/dev/fb0</code> device in Linux
* LVDS1 is mapped to the corresponding device driver in Linux, depending on the <code>ldb</code> peripheral configuration in the device tree. The default value is ''disabled'' but can be mapped to <code>/dev/fb2</code> (second and independent LCD panel) or can be the second LVDs channel for a dual-channel LCD panel configuration (like a 1920x1080 DUAL LVDS channel LCD panel)
=== Power sequence ===
Most of the LCD panels have many supplies and need a specific timing to power the rails and start the signals.
The Evaluation Kit provides GPIO controlled power rails that can be leveraged both at bootloader and kernel level to meet any specifications.
The following sections describe the available rails:
==== 3V3_LCD ====
The most common voltage to supply the LCD panel internal logic:
* rail 3V3_LCD0 is enabled by <code>GPIO1_IO00</code>
* rail 3V3_LCD1 is enabled by <code>GPIO1_IO02</code>
==== 5V_LCD ====
The most common voltage to supply the LCD panel backlight:
* rail 5V_LCD0 is enabled by <code>SD3_DATA1</code>
* rail 5V_LCD1 is enabled by <code>SD3_DATA0</code>
=== Device usage ===