Open main menu

DAVE Developer's Wiki β

Changes

AURA SOM/AURA Hardware/Pinout Table

45 bytes removed, 15:47, 17 May 2023
Pinout Table ODD pins declaration
| rowspan="8" |CPU.GPIO_IO06
| rowspan="8" |L20
| rowspan="8" |NVCC_GPIONVCC_3V3
| rowspan="8" |IO
| rowspan="8" |
| rowspan="8" |CPU.GPIO_IO18
| rowspan="8" |R18
| rowspan="8" |NVCC_GPIONVCC_3V3
| rowspan="8" |IO
| rowspan="8" |
| rowspan="8" |CPU.GPIO_IO09
| rowspan="8" |M21
| rowspan="8" |NVCC_GPIONVCC_3V3
| rowspan="8" |IO
| rowspan="8" |
| rowspan="8" |CPU.GPIO_IO08
| rowspan="8" |M20
| rowspan="8" |NVCC_GPIONVCC_3V3
| rowspan="8" |IO
| rowspan="8" |
| rowspan="8" |CPU.GPIO_IO10
| rowspan="8" |N17
| rowspan="8" |NVCC_GPIONVCC_3V3
| rowspan="8" |IO
| rowspan="8" |
| rowspan="8" |CPU.GPIO_IO11
| rowspan="8" |N18
| rowspan="8" |NVCC_GPIONVCC_3V3
| rowspan="8" |IO
| rowspan="8" |
| rowspan="4" |CPU.GPIO_IO11
| rowspan="4" |T16
| rowspan="4" |NVCC_GPIONVCC_3V3
| rowspan="4" |IO
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
| rowspan="4" |CPU.GPIO_IO11
| rowspan="4" |V14
| rowspan="4" |NVCC_GPIONVCC_3V3
| rowspan="4" |IO
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
| rowspan="4" |CPU.GPIO_IO12
| rowspan="4" |U14
| rowspan="4" |NVCC_GPIONVCC_3V3
| rowspan="4" |IO
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
| rowspan="4" |CPU.GPIO_IO13
| rowspan="4" |T14
| rowspan="4" |NVCC_GPIONVCC_3V3
| rowspan="4" |IO
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
| rowspan="4" |CPU.GPIO_IO21
| rowspan="4" |U16
| rowspan="4" |NVCC_GPIONVCC_3V3
| rowspan="4" |IO
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
| rowspan="4" |CPU.GPIO_IO20
| rowspan="4" |V16
| rowspan="4" |NVCC_GPIONVCC_3V3
| rowspan="4" |IO
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
| rowspan="5" |CPU.SD2_DATA0
| rowspan="5" |Y18
| rowspan="5" |NVCC_GPIONVCC_3V3
| rowspan="5" |IO
| rowspan="5" |
| rowspan="5" |CPU.SD2_DATA1
| rowspan="5" |AA18
| rowspan="5" |NVCC_GPIONVCC_3V3
| rowspan="5" |IO
| rowspan="5" |
| rowspan="5" |CPU.SD2_DATA2
| rowspan="5" |Y20
| rowspan="5" |NVCC_GPIONVCC_3V3
| rowspan="5" |IO
| rowspan="5" |
| rowspan="5" |CPU.SD2_DATA3
| rowspan="5" |AA20
| rowspan="5" |NVCC_GPIONVCC_3V3
| rowspan="5" |IO
| rowspan="5" |
| rowspan="6" |CPU.SD2_CMD
| rowspan="6" |Y19
| rowspan="6" |NVCC_GPIONVCC_3V3
| rowspan="6" |IO
| rowspan="6" |
| rowspan="5" |CPU.SD2_CLK
| rowspan="5" |AA19
| rowspan="5" |NVCC_GPIONVCC_3V3
| rowspan="5" |IO
| rowspan="5" |
| rowspan="8" |CPU.GPIO_IO14
| rowspan="8" |P20
| rowspan="8" |NVCC_GPIONVCC_3V3
| rowspan="8" |IO
| rowspan="8" |
| rowspan="8" |CPU.GPIO_IO15
| rowspan="8" |P21
| rowspan="8" |NVCC_GPIONVCC_3V3
| rowspan="8" |IO
| rowspan="8" |
| rowspan="5" |CPU.UART2_TXD//BOOT1
| rowspan="5" |F21
| rowspan="5" |NVCC_GPIONVCC_3V3
| rowspan="5" |IO
| rowspan="5" |Used as default console for Cortex-M33
| rowspan="6" |CPU.UART2_RXD
| rowspan="6" |F20
| rowspan="6" |NVCC_GPIONVCC_3V3
| rowspan="6" |IO
| rowspan="6" |Used as default console for Cortex-M33
| rowspan="5" |CPU.SD2_VSELECT
| rowspan="5" |V18
| rowspan="5" |NVCC_GPIONVCC_3V3
| rowspan="5" |IO
| rowspan="5" |
| rowspan="4" |CPU.SD2_RESET_B
| rowspan="4" |AA17
| rowspan="4" |NVCC_GPIONVCC_3V3
| rowspan="4" |IO
| rowspan="4" |
| rowspan="5" |CPU.I2C1_SCL
| rowspan="5" |C20
| rowspan="5" |NVCC_GPIONVCC_3V3
| rowspan="5" |IO
| rowspan="5" |
| rowspan="5" |CPU.I2C1_SDA
| rowspan="5" |C21
| rowspan="5" |NVCC_GPIONVCC_3V3
| rowspan="5" |IO
| rowspan="5" |
| rowspan="6" |CPU.SAI1_TXD0//BOOT3
| rowspan="6" |H21
| rowspan="6" |NVCC_GPIONVCC_3V3
| rowspan="6" |IO
| rowspan="6" |
| rowspan="6" |CPU.SAI1_TXC
| rowspan="6" |G20
| rowspan="6" |NVCC_GPIONVCC_3V3
| rowspan="6" |IO
| rowspan="6" |
| rowspan="1" |CPU.ADC_IN0
| rowspan="1" |B19
| rowspan="1" |NVCC_GPIONVCC_3V3
| rowspan="1" |IO
| rowspan="1" |
| rowspan="1" |CPU.ADC_IN1
| rowspan="1" |A20
| rowspan="1" |NVCC_GPIONVCC_3V3
| rowspan="1" |IO
| rowspan="1" |
| rowspan="1" |CPU.ADC_IN2
| rowspan="1" |B20
| rowspan="1" |NVCC_GPIONVCC_3V3
| rowspan="1" |IO
| rowspan="1" |
| rowspan="1" |CPU.ADC_IN3
| rowspan="1" |B21
| rowspan="1" |NVCC_GPIONVCC_3V3
| rowspan="1" |IO
| rowspan="1" |
| rowspan="5" |CPU.I2C2_SDA<br>PMIC.SDA
| rowspan="5" |D21<br>42
| rowspan="5" |NVCC_GPIONVCC_3V3
| rowspan="5" |IO
| rowspan="5" |
| rowspan="7" |CPU.I2C2_SCL<br>PMIC.SCL
| rowspan="7" |D20<br>41
| rowspan="7" |NVCC_GPIONVCC_3V3
| rowspan="7" |IO
| rowspan="7" |
| rowspan="5" |CPU.GPIO_IO08
| rowspan="5" |M20
| rowspan="5" |NVCC_GPIONVCC_3V3
| rowspan="5" |IO
| rowspan="5" |
| rowspan="8" |CPU.GPIO_IO00
| rowspan="8" |J21
| rowspan="8" |NVCC_GPIONVCC_3V3
| rowspan="8" |IO
| rowspan="8" |
| rowspan="8" |CPU.GPIO_IO03
| rowspan="8" |K21
| rowspan="8" |NVCC_GPIONVCC_3V3
| rowspan="8" |IO
| rowspan="8" |
| rowspan="8" |CPU.GPIO_IO01
| rowspan="8" |K21
| rowspan="8" |NVCC_GPIONVCC_3V3
| rowspan="8" |IO
| rowspan="8" |
| rowspan="5" |CPU.UART1_TXD//BOOT0
| rowspan="5" |E21
| rowspan="5" |NVCC_GPIONVCC_3V3
| rowspan="5" |IO
| rowspan="5" |Used as default Linux console (Cortex-A55)
| rowspan="5" |CPU.UART1_RXD
| rowspan="5" |E20
| rowspan="5" |NVCC_GPIONVCC_3V3
| rowspan="5" |IO
| rowspan="5" |Used as default Linux console (Cortex-A55)
| rowspan="8" |CPU.GPIO_IO12
| rowspan="8" |N20
| rowspan="8" |NVCC_GPIONVCC_3V3
| rowspan="8" |IO
| rowspan="8" |
| rowspan="8" |CPU.GPIO_IO13
| rowspan="8" |N21
| rowspan="8" |NVCC_GPIONVCC_3V3
| rowspan="8" |IO
| rowspan="8" |
| rowspan="8" |CPU.GPIO_IO02
| rowspan="8" |K21
| rowspan="8" |NVCC_GPIONVCC_3V3
| rowspan="8" |IO
| rowspan="8" |
| rowspan="7" |CPU.PDM_BIT_STREAM0
| rowspan="7" |J17
| rowspan="7" |NVCC_GPIONVCC_3V3
| rowspan="7" |IO
| rowspan="7" |
| rowspan="5" |CPU.PDM_CLK
| rowspan="5" |G17
| rowspan="5" |NVCC_GPIONVCC_3V3
| rowspan="5" |IO
| rowspan="5" |
8,226
edits