Bureaucrats, dave_user, Administrators
8,226
edits
Changes
→Pinout Table EVEN pins declaration
|-
|Pin ALT-4
|FELXIO2FLEXIO2.FLEXIO[30]
|-
|Pin ALT-5
|-
|Pin ALT-4
|FELXIO2FLEXIO2.FLEXIO[31]
|-
|Pin ALT-5
|-
|Pin ALT-4
|FELXIO1FLEXIO1.FLEXIO[30]
|-
|Pin ALT-5
|-
|Pin ALT-4
|FELXIO1FLEXIO1.FLEXIO[31]
|-
|Pin ALT-5
|-
|J1.100
|DGND
|DGND
| -
| -
|G
|
|
|
|-
|J1.102
|CSI_CLK_N
|CPU.MIPI_CSI1_CLK_N
|D10
|VDD_ANA_1V8
|D
|
|
|
|-
|J1.104
|CSI_CLK_P
|CPU.MIPI_CSI1_CLK_P
|E10
|VDD_ANA_1V8
|D
|
|
|
|-
|J1.106
|CSI_D0_N
|CPU.MIPI_CSI1_D0_N
|A11
|VDD_ANA_1V8
|D
|
|
|
|-
|J1.108
|CSI_D0_P
|CPU.MIPI_CSI1_D0_P
|B11
|VDD_ANA_1V8
|D
|
|
|
|-
|J1.110
|CSI_D1_N
|CPU.MIPI_CSI1_D1_N
|A10
|VDD_ANA_1V8
|D
|
|
|
|-
|J1.112
|CSI_D1_P
|CPU.MIPI_CSI1_D1_P
|B10
|VDD_ANA_1V8
|D
|
|
|
|-
|J1.114
|USB1_RX_N
|CPU.USB1_RX_N
|A12
|VDD_ANA_1V8
|D
|Only for i.MX933x/i.MX935x
|
|
|-
|J1.116
|USB1_RX_P
|CPU.USB1_RX_P
|B12
|VDD_ANA_1V8
|D
|Only for i.MX933x/i.MX935x
|
|
|-
|J1.118
|USB1_TX_N
|CPU.USB1_TX_N
|A13
|VDD_ANA_1V8
|D
|Only for i.MX933x/i.MX935x
|
|
|-
|J1.120
|USB1_TX_P
|CPU.USB1_TX_P
|B13
|VDD_ANA_1V8
|D
|Only for i.MX933x/i.MX935x
|
|
|-
|J1.122
|DGND
|DGND
| -
| -
|G
|
|
|
|-
| rowspan="6" |J1.124
| rowspan="6" |ENET1_MDC
| rowspan="6" |CPU.ENET1_MDC
| rowspan="6" |AA11
| rowspan="6" |NVCC_3V3
| rowspan="6" |IO
| rowspan="6" |
|Pin ALT-0
|ENET_QOS.MDC
|-
|Pin ALT-1
|UART3.DCR_B
|-
|Pin ALT-2
|I3C2.SCL
|-
|Pin ALT-3
|USB1.OTG_ID
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[0]
|-
|Pin ALT-5
|GPIO4.IO00
|-
| rowspan="6" |J1.126
| rowspan="6" |ENET1_MDIO
| rowspan="6" |CPU.ENET1_MDIO
| rowspan="6" |AA10
| rowspan="6" |NVCC_3V3
| rowspan="6" |IO
| rowspan="6" |
|Pin ALT-0
|ENET_QOS.MDIO
|-
|Pin ALT-1
|UART3.RIN_B
|-
|Pin ALT-2
|I3C2.SDA
|-
|Pin ALT-3
|USB1.OTG_PWR
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[1]
|-
|Pin ALT-5
|GPIO4.IO01
|-
| rowspan="3" |J1.128
| rowspan="3" |SD1_CLK
| rowspan="3" |CPU.SD1_CLK
| rowspan="3" |Y11
| rowspan="3" |NVCC_3V3
| rowspan="3" |IO
| rowspan="3" |
|Pin ALT-0
|USDHC1.CLK
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[8]
|-
|Pin ALT-5
|GPIO3_IO08
|-
| rowspan="3" |J1.130
| rowspan="3" |SD1_CMD
| rowspan="3" |CPU.SD1_CMD
| rowspan="3" |AA12
| rowspan="3" |NVCC_3V3
| rowspan="3" |IO
| rowspan="3" |
|Pin ALT-0
|USDHC1.CMD
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[9]
|-
|Pin ALT-5
|GPIO3_IO09
|-
|J1.132
|ETH1_LED5
|LAN.LED5/GPIO4
|13
|NVCC_3V3
|O
|
|
|
|-
| rowspan="4" |J1.134
| rowspan="4" |SD1_STROBE
| rowspan="4" |CPU.SD1_CLK
| rowspan="4" |Y11
| rowspan="4" |NVCC_3V3
| rowspan="4" |IO
| rowspan="4" |
|Pin ALT-0
|USDHC1.CLK
|-
|Pin ALT-1
|FLEXSPI.A_DQS
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[18]
|-
|Pin ALT-5
|GPIO3_IO018
|-
|J1.136
|
|
|
|
|
|
|
|
|-
| rowspan="3" |J1.138
| rowspan="3" |SD1_DATA0
| rowspan="3" |CPU.SD1_DATA0
| rowspan="3" |AA14
| rowspan="3" |NVCC_3V3
| rowspan="3" |IO
| rowspan="3" |
|Pin ALT-0
|USDHC1.DATA0
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[10]
|-
|Pin ALT-5
|GPIO3_IO10
|-
| rowspan="3" |J1.140
| rowspan="3" |SD1_DATA1
| rowspan="3" |CPU.SD1_DATA1
| rowspan="3" |AA15
| rowspan="3" |NVCC_3V3
| rowspan="3" |IO
| rowspan="3" |
|Pin ALT-0
|USDHC1.DATA1
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[11]
|-
|Pin ALT-5
|GPIO3_IO11
|-
| rowspan="3" |J1.142
| rowspan="3" |SD1_DATA2
| rowspan="3" |CPU.SD1_DATA2
| rowspan="3" |AA16
| rowspan="3" |NVCC_3V3
| rowspan="3" |IO
| rowspan="3" |
|Pin ALT-0
|USDHC1.DATA2
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[12]
|-
|Pin ALT-5
|GPIO3_IO12
|-
| rowspan="3" |J1.144
| rowspan="3" |SD1_DATA3
| rowspan="3" |CPU.SD1_DATA3
| rowspan="3" |Y11
| rowspan="3" |NVCC_3V3
| rowspan="3" |IO
| rowspan="3" |
|Pin ALT-0
|USDHC1.DATA3
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[13]
|-
|Pin ALT-5
|GPIO3_IO13
|-
|J1.146
|DGND
|DGND
| -
| -
|G
|
|
|
|-
| rowspan="4" |J1.148
| rowspan="4" |SD1_DATA4
| rowspan="4" |CPU.SD1_DATA4
| rowspan="4" |Y13
| rowspan="4" |NVCC_3V3
| rowspan="4" |IO
| rowspan="4" |
|Pin ALT-0
|USDHC1.DATA4
|-
|Pin ALT-1
|FLEXSPI.A_DATA[4]
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[14]
|-
|Pin ALT-5
|GPIO3_IO14
|-
| rowspan="4" |J1.150
| rowspan="4" |SD1_DATA5
| rowspan="4" |CPU.SD1_DATA5
| rowspan="4" |Y14
| rowspan="4" |NVCC_3V3
| rowspan="4" |IO
| rowspan="4" |
|Pin ALT-0
|USDHC1.DATA5
|-
|Pin ALT-1
|FLEXSPI.A_DATA[5]
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[15]
|-
|Pin ALT-5
|GPIO3_IO15
|-
| rowspan="4" |J1.152
| rowspan="4" |SD1_DATA5
| rowspan="4" |CPU.SD1_DATA6
| rowspan="4" |Y15
| rowspan="4" |NVCC_3V3
| rowspan="4" |IO
| rowspan="4" |
|Pin ALT-0
|USDHC1.DATA6
|-
|Pin ALT-1
|FLEXSPI.A_DATA[6]
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[16]
|-
|Pin ALT-5
|GPIO3_IO16
|-
| rowspan="4" |J1.154
| rowspan="4" |SD1_DATA7
| rowspan="4" |CPU.SD1_DATA7
| rowspan="4" |Y16
| rowspan="4" |NVCC_3V3
| rowspan="4" |IO
| rowspan="4" |
|Pin ALT-0
|USDHC1.DATA7
|-
|Pin ALT-1
|FLEXSPI.A_DATA[7]
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[17]
|-
|Pin ALT-5
|GPIO3_IO17
|-
| rowspan="4" |J1.156
| rowspan="4" |ENET2_TD3
| rowspan="4" |CPU.ENET2_TD3
| rowspan="4" |T10
| rowspan="4" |NVCC_3V3
| rowspan="4" |IO
| rowspan="4" |
|Pin ALT-0
|ENET2.RGMII_TD3
|-
|Pin ALT-2
|SAI2.RX_DATA[0]
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[16]
|-
|Pin ALT-5
|GPIO4.IO16
|-
| rowspan="5" |J1.158
| rowspan="5" |ENET2_TD2
| rowspan="5" |CPU.ENET2_TD2
| rowspan="5" |V8
| rowspan="5" |NVCC_3V3
| rowspan="5" |IO
| rowspan="5" |
|Pin ALT-0
|ENET2.RGMII_TD2
|-
|Pin ALT-1
|ENET2.TX_CLK // CCMSRCGPMCMIX.ENET_REF_CLK_ROOT
|-
|Pin ALT-2
|SAI2.RX_DATA[1]
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[17]
|-
|Pin ALT-5
|GPIO4.IO17
|-
| rowspan="5" |J1.160
| rowspan="5" |ENET2_TD1
| rowspan="5" |CPU.ENET2_TD1
| rowspan="5" |U8
| rowspan="5" |NVCC_3V3
| rowspan="5" |IO
| rowspan="5" |
|Pin ALT-0
|ENET2.RGMII_TD1
|-
|Pin ALT-1
|UART4.RTS_B
|-
|Pin ALT-2
|SAI2.RX_DATA[2]
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[18]
|-
|Pin ALT-5
|GPIO4.IO18
|-
| rowspan="5" |J1.162
| rowspan="5" |ENET2_TD0
| rowspan="5" |CPU.ENET2_TD0
| rowspan="5" |T8
| rowspan="5" |NVCC_3V3
| rowspan="5" |IO
| rowspan="5" |
|Pin ALT-0
|ENET2.RGMII_TD0
|-
|Pin ALT-1
|UART4.TX
|-
|Pin ALT-2
|SAI2.RX_DATA[3]
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[19]
|-
|Pin ALT-5
|GPIO4.IO19
|-
|J1.164
|DGND
|DGND
| -
| -
|G
|
|
|
|-
| rowspan="5" |J1.166
| rowspan="5" |ENET2_XC
| rowspan="5" |CPU.ENET2_XC
| rowspan="5" |U6
| rowspan="5" |NVCC_3V3
| rowspan="5" |IO
| rowspan="5" |
|Pin ALT-0
|ENET2.RGMI_TXC
|-
|Pin ALT-1
|ENET2.TX_ER
|-
|Pin ALT-2
|SAI2.TX_BCLK
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[21]
|-
|Pin ALT-5
|GPIO4.IO21
|-
| rowspan="5" |J1.168
| rowspan="5" |ENET2_TX_CTL
| rowspan="5" |CPU.ENET2_TX_CTL
| rowspan="5" |V6
| rowspan="5" |NVCC_3V3
| rowspan="5" |IO
| rowspan="5" |
|Pin ALT-0
|ENET2.RGMI_TX_CTL
|-
|Pin ALT-1
|UART4.DTR_B
|-
|Pin ALT-2
|SAI2.TX_SYNC
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[20]
|-
|Pin ALT-5
|GPIO4.IO20
|-
| rowspan="5" |J1.170
| rowspan="5" |ENET2_MDC
| rowspan="5" |CPU.ENET2_MDC
| rowspan="5" |Y7
| rowspan="5" |NVCC_3V3
| rowspan="5" |IO
| rowspan="5" |
|Pin ALT-0
|ENET2.MDC
|-
|Pin ALT-1
|UART4.DCR_B
|-
|Pin ALT-2
|SAI2.RX_SYNC
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[14]
|-
|Pin ALT-5
|GPIO4.IO14
|-
| rowspan="5" |J1.172
| rowspan="5" |ENET2_MDIO
| rowspan="5" |CPU.ENET2_MDIO
| rowspan="5" |AA6
| rowspan="5" |NVCC_3V3
| rowspan="5" |IO
| rowspan="5" |
|Pin ALT-0
|ENET2.MDIO
|-
|Pin ALT-1
|UART4.RIN_B
|-
|Pin ALT-2
|SAI2.RX_BCLK
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[15]
|-
|Pin ALT-5
|GPIO4.IO15
|-
| rowspan="5" |J1.174
| rowspan="5" |ENET2_RX_CTL
| rowspan="5" |CPU.ENET2_RX_CTL
| rowspan="5" |Y4
| rowspan="5" |NVCC_3V3
| rowspan="5" |IO
| rowspan="5" |
|Pin ALT-0
|ENET2.RGMII_RX_CTL
|-
|Pin ALT-1
|UART4.DSR_B
|-
|Pin ALT-2
|SAI2.TX_DATA[0]
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[22]
|-
|Pin ALT-5
|GPIO4.IO22
|-
| rowspan="5" |J1.176
| rowspan="5" |ENET2_RD0
| rowspan="5" |CPU.ENET2_RD0
| rowspan="5" |AA4
| rowspan="5" |NVCC_3V3
| rowspan="5" |IO
| rowspan="5" |
|Pin ALT-0
|ENET2.RGMII_RD0
|-
|Pin ALT-1
|UART4.RX
|-
|Pin ALT-2
|SAI2.TX_DATA[2]
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[24]
|-
|Pin ALT-5
|GPIO4.IO24
|-
| rowspan="5" |J1.178
| rowspan="5" |ENET2_RD1
| rowspan="5" |CPU.ENET2_RD1
| rowspan="5" |Y5
| rowspan="5" |NVCC_3V3
| rowspan="5" |IO
| rowspan="5" |
|Pin ALT-0
|ENET2.RGMII_RD1
|-
|Pin ALT-1
|SPDIF1.IN
|-
|Pin ALT-2
|SAI2.TX_DATA[3]
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[25]
|-
|Pin ALT-5
|GPIO4.IO25
|-
| rowspan="6" |J1.180
| rowspan="6" |ENET2_RD2
| rowspan="6" |CPU.ENET2_RD2
| rowspan="6" |AA5
| rowspan="6" |NVCC_3V3
| rowspan="6" |IO
| rowspan="6" |
|Pin ALT-0
|ENET2.RGMII_RD1
|-
|Pin ALT-1
|UART4.CTS_B
|-
|Pin ALT-2
|SAI2.MCLK
|-
|Pin ALT-3
|MQS2.RIGHT
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[26]
|-
|Pin ALT-5
|GPIO4.IO26
|-
| rowspan="6" |J1.182
| rowspan="6" |ENET2_RD3
| rowspan="6" |CPU.ENET2_RD3
| rowspan="6" |Y6
| rowspan="6" |NVCC_3V3
| rowspan="6" |IO
| rowspan="6" |
|Pin ALT-0
|ENET2.RGMII_RD3
|-
|Pin ALT-1
|SPDIF1.OUT
|-
|Pin ALT-2
|SPDIF1.N
|-
|Pin ALT-3
|MQS2.LEFT
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[27]
|-
|Pin ALT-5
|GPIO4.IO27
|-
| rowspan="5" |J1.184
| rowspan="5" |ENET2_RXC
| rowspan="5" |CPU.ENET2_RXC
| rowspan="5" |AA3
| rowspan="5" |NVCC_3V3
| rowspan="5" |IO
| rowspan="5" |
|Pin ALT-0
|ENET2.RGMII_RXC
|-
|Pin ALT-1
|ENET2.RX_ER
|-
|Pin ALT-2
|SAI2.TX_DATA[1]
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[23]
|-
|Pin ALT-5
|GPIO4.IO23
|-
|J1.186
|USB1_VBUS
|CPU.USB1_VBUS
|F13
|NVCC_3V3
|D
|(3V3 reference signal)
|
|
|-
|J1.188
|USB2_VBUS
|CPU.USB2_VBUS
|E14
|NVCC_3V3
|D
|(3V3 reference signal)
|
|
|-
|J1.190
|DGND
|DGND
| -
| -
|G
|
|
|
|-
|J1.192
|USB1_ID
|CPU.USB1_ID
|C11
|
|D
|
|
|
|-
|J1.194
|USB2_ID
|CPU.USB2_ID
|E12
|
|D
|
|
|
|-
|J1.196
|USB1_DN
|CPU.USB1_DN
|A14
|
|D
|
|
|
|-
|J1.198
|USB1_DP
|CPU.USB1_DP
|B14
|
|D
|
|
|
|-
|J1.200
|USB2_DP
|CPU.USB2_DP
|B15
|
|D
|
|
|
|-
|J1.202
|USB2_DN
|CPU.USB2_DN
|A15
|
|D
|
|
|
|-
|J1.204
|DGND
|DGND