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→Pinout Table ODD pins declaration
|3.3
|Voltage generated by the internal PSU. See [[AURA_SOM/AXEL_Lite_Hardware/Power_and_Reset/Power_Supply_Unit_(PSU)_and_recommended_power-up_sequence | Power Supply Unit (PSU)]] wiki page
|-
|VDD_ANA_1V8
|1.8
|
|-
|}
|Pin ALT-7
|FLEXIO1.FLEXIO[8]
|-
|
|
|
|
|
|
|
|
|
|-
|J1.131
|DGND
|DGND
| -
| -
|G
|
|
|
|-
|J1.133
|LVDS_CLK_N
|CPU.LVDS_CLK_N
|A3
|VDD_ANA_1V8
|D
|
|
|
|-
|J1.135
|LVDS_CLK_P
|CPU.LVDS_CLK_P
|B3
|VDD_ANA_1V8
|D
|
|
|
|-
|J1.137
|LVDS_TX0_N
|CPU.LVDS_TX0_N
|A5
|VDD_ANA_1V8
|D
|
|
|
|-
|J1.139
|LVDS_TX0_P
|CPU.LVDS_TX0_P
|B5
|VDD_ANA_1V8
|D
|
|
|
|-
|J1.141
|LVDS_TX1_N
|CPU.LVDS_TX1_N
|A4
|VDD_ANA_1V8
|D
|
|
|
|-
|J1.143
|LVDS_TX1_P
|CPU.LVDS_TX1_P
|B4
|VDD_ANA_1V8
|D
|
|
|
|-
|J1.145
|LVDS_TX2_N
|CPU.LVDS_TX2_N
|A2
|VDD_ANA_1V8
|D
|
|
|
|-
|J1.147
|LVDS_TX2_P
|CPU.LVDS_TX2_P
|B2
|VDD_ANA_1V8
|D
|
|
|
|-
|J1.149
|LVDS_TX3_N
|CPU.LVDS_TX3_N
|B1
|VDD_ANA_1V8
|D
|
|
|
|-
|J1.151
|LVDS_TX3_P
|CPU.LVDS_TX3_P
|C1
|VDD_ANA_1V8
|D
|
|
|
|-
|J1.153
|DGND
|DGND
| -
| -
|G
|
|
|
|-
|J1.155
|DSI_CLK_N
|CPU.DSI_CLK_N
|D6
|VDD_ANA_1V8
|D
|
|
|
|-
|J1.157
|DSI_CLK_P
|CPU.DSI_CLK_P
|E6
|VDD_ANA_1V8
|D
|
|
|
|-
|J1.159
|DSI_TX0_N
|CPU.DSI_TX0_N
|A6
|VDD_ANA_1V8
|D
|
|
|
|-
|J1.161
|DSI_TX0_P
|CPU.DSI_TX0_P
|B6
|VDD_ANA_1V8
|D
|
|
|
|-
|J1.163
|DSI_TX1_N
|CPU.DSI_TX1_N
|A7
|VDD_ANA_1V8
|D
|
|
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|-
|J1.165
|DSI_TX1_P
|CPU.DSI_TX1_P
|B7
|VDD_ANA_1V8
|D
|
|
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|-
|J1.167
|DSI_TX2_N
|CPU.DSI_TX2_N
|A8
|VDD_ANA_1V8
|D
|
|
|
|-
|J1.169
|DSI_TX2_P
|CPU.DSI_TX2_P
|B8
|VDD_ANA_1V8
|D
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|-
|J1.171
|DSI_TX3_N
|CPU.DSI_TX3_N
|A9
|VDD_ANA_1V8
|D
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|
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|-
|J1.173
|DSI_TX3_P
|CPU.DSI_TX3_P
|B9
|VDD_ANA_1V8
|D
|
|
|
|-
|J1.175
|DGND
|DGND
| -
| -
|G
|
|
|
|-
| rowspan="5" |J1.177
| rowspan="5" |SD2_CD_B
| rowspan="5" |CPU.GPIO_IO08
| rowspan="5" |M20
| rowspan="5" |NVCC_GPIO
| rowspan="5" |IO
| rowspan="5" |
|Pin ALT-0
|USDHC2.CD_B
|-
|Pin ALT-1
|ENET_QOS.1588_EVENT0_IN
|-
|Pin ALT-2
|I2C3.SCL
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[0]
|-
|Pin ALT-5
|GPIO3_IO00
|}