Bureaucrats, dave_user, Administrators
8,282
edits
Changes
Created page with "<section begin=History/> {| style="border-collapse:collapse; " !colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History |- !style="border-le..."
<section begin=History/>
{| style="border-collapse:collapse; "
!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History
|-
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes
|-
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|2023/09/13
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|First release
|-
|}
<section end=History/>
__FORCETOC__
<section begin=Body/>
==Peripheral Watchdog ==
WDOG is an independent timer that is available for system use. It provides a safety feature to ensure that the software is executing as planned and that the CPU is not stuck in an infinite loop or executing unintended code.
The Watchdog module available on AURA is based on i.MX93 SoC. The SOC has five WDOG timers:
* WDOG1 and WDOG2 are reset whenever the Cortex-M33 is reset
=== Description ===
The WDOG port supports the following features:
* Configurable clock source inputs independent of the bus clock
* Programmable 16-bit timeout value
* Window mode option for the refresh mechanism
* Optional timeout interrupt to allow post-processing diagnostics
* Write-once-after-reset configuration fields
===Pin mapping===
The Pin mapping is described in the [[AURA SOM/AURA Hardware/Pinout_Table | Pinout table section]]
----
[[Category:AURA]]
{| style="border-collapse:collapse; "
!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History
|-
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes
|-
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|2023/09/13
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|First release
|-
|}
<section end=History/>
__FORCETOC__
<section begin=Body/>
==Peripheral Watchdog ==
WDOG is an independent timer that is available for system use. It provides a safety feature to ensure that the software is executing as planned and that the CPU is not stuck in an infinite loop or executing unintended code.
The Watchdog module available on AURA is based on i.MX93 SoC. The SOC has five WDOG timers:
* WDOG1 and WDOG2 are reset whenever the Cortex-M33 is reset
=== Description ===
The WDOG port supports the following features:
* Configurable clock source inputs independent of the bus clock
* Programmable 16-bit timeout value
* Window mode option for the refresh mechanism
* Optional timeout interrupt to allow post-processing diagnostics
* Write-once-after-reset configuration fields
===Pin mapping===
The Pin mapping is described in the [[AURA SOM/AURA Hardware/Pinout_Table | Pinout table section]]
----
[[Category:AURA]]