Bureaucrats, dave_user, Administrators
8,226
edits
Changes
Created page with "<section begin="History" /> {| style="border-collapse:collapse; " ! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History |- ! style="bo..."
<section begin="History" />
{| style="border-collapse:collapse; "
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
|-
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |2023/09/13
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
|-
|}
<section end="History" />
<section begin="Body" />
==Peripheral USB ==
The two USB interfaces available on AURA are based on iMX93 SoC which includes two instances of USB 2.0 Controllers and PHY that can be used as USB OTG port, USB Host port or USB Device port.
Universal Serial Bus (USB) is an industry-standard that establishes specifications for cables and connectors and protocols for connection, communication and power supply (interfacing) between computers, peripherals and other computers.
=== Description ===
There are two USB 2.0 controller cores in this chip:
* Controller Core 0 is also named ''USB1''
* Controller Core 1 is also named ''USB2''
Both USB 2.0 Controllers provide the following features:
* High-Speed/Full-Speed/Low-Speed (HS/FS/LS) OTG core
* HS/FS/LS UTMI compliant interface
* HS, FS, and LS operation in HOST mode (with UTMI transceiver)
* HS and FS operation in Peripheral mode (with UTMI transceiver)
* Hardware support for OTG signaling, session request protocol, and host negotiation protocol
* 8 bidirectional endpoints
=== VBUS detection ===
On the AURA external connector, the USB[1..2]_VBUS pins are present to detect that the USB is enabled end therefore power the internal USB PHY.
===Pin mapping===
The Pin mapping is described in the [[AURA SOM/AURA Hardware/Pinout_Table | Pinout table section]]
<section end="Body" />
----
[[Category:AURA]]
{| style="border-collapse:collapse; "
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
|-
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |2023/09/13
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
|-
|}
<section end="History" />
<section begin="Body" />
==Peripheral USB ==
The two USB interfaces available on AURA are based on iMX93 SoC which includes two instances of USB 2.0 Controllers and PHY that can be used as USB OTG port, USB Host port or USB Device port.
Universal Serial Bus (USB) is an industry-standard that establishes specifications for cables and connectors and protocols for connection, communication and power supply (interfacing) between computers, peripherals and other computers.
=== Description ===
There are two USB 2.0 controller cores in this chip:
* Controller Core 0 is also named ''USB1''
* Controller Core 1 is also named ''USB2''
Both USB 2.0 Controllers provide the following features:
* High-Speed/Full-Speed/Low-Speed (HS/FS/LS) OTG core
* HS/FS/LS UTMI compliant interface
* HS, FS, and LS operation in HOST mode (with UTMI transceiver)
* HS and FS operation in Peripheral mode (with UTMI transceiver)
* Hardware support for OTG signaling, session request protocol, and host negotiation protocol
* 8 bidirectional endpoints
=== VBUS detection ===
On the AURA external connector, the USB[1..2]_VBUS pins are present to detect that the USB is enabled end therefore power the internal USB PHY.
===Pin mapping===
The Pin mapping is described in the [[AURA SOM/AURA Hardware/Pinout_Table | Pinout table section]]
<section end="Body" />
----
[[Category:AURA]]