|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|{{oldid|nnnn|yyyy2023/mm09/dd}}13|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|TBD|-!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000"|yyyy/mm/dd!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000"|TBD|-First release

''TBDThe AURA SOM based on i.MX93 SoC has two MIPI interfaces: sostituire le sezioni con le informazioni sull'uso della periferica''''Nell'esempio di seguito c'è la descrizione dell'interfaccia HDMI''* One 4-lane MIPI-DPHY DSI Tx PHY and MIPI-DSI Controller* One 2-lane MIPI-DPHY CSI Rx PHY and MIPI-CSI Controller compliant to MIPI-DSI specification v1.2 and MIPI-DPHY specification v1.2

The MIPI -DSI controller supports the following features:* Configurable selection of system interfaces: ** AMBA APB for control and optional support for Generic and DCS commands** Display Pixel Interface (DPI) for Video mode interface (optional)* Fault recovery mechanisms* Ultra Low-Power mode with PLL disabled* DPI features:** DPI signals programmable polarity** Extended resolutions beyond the DPI standard** Maximum resolution limited by available on AURA DSI physical link bandwidth, which is based on xxxxx ''TBD:SOC name'' SoC. determined by the number of physical (up to 2048x1080@60Hz 24bpp with 4 lanes)lanes and the maximum speed that they can achieve* Video pattern generator

The MIPI port CSI-2 controller receives data from a CSI-2 compliant camera sensor and supports the following standards and featuresblocks:* PHY-Protocol Interface (PPI) Data Processor and Pattern Generator* HighDe-Definition Multimedia Interface Specification, Version 1.4a scrambler* PHY Adaptation Layer* Support for up to 1080p Image Pixel Interface (IPI) Controller (48-bit parallel bus operating at 60Hz HDTV display resolutions and up to QXGA graphic display resolutions. pixel clock rate)* Support for 4k x 2k * Two operating modes: Camera Timing and 3D video formats Controller Timing * Support for up to * Generates pixel stream (48 or 16-bit Deep Color modes)** data formats: YUV, RGB, RAW, User defined