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BoraEVB-Lite

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~~{{WorkInProgress}}{{InfoBoxTop}}{{Applies To Bora}}{{InfoBoxBottom}}~~ {{WarningMessage|text=~~The information here~~ This carrier board is '''obsolete''' and its shipment is discontinued. Starting from version 2.0.0 of the BELK, the official carrier board provided ~~are preliminary and subject to change~~with the BELK is the [[BoraEVB]].This wiki page remains published as reference, but won't be updated anymore}}

== Connectors pinout ==

=== Power supply - J7 ===

Power is provided through the J7 connector.

{| class="wikitable"

|-

!Pin#

!Pin name

!Function

!Notes

|-

|1 || VIN || Power supply || Nominal: +12V

|-

|2 || DGND || Ground || -

|-

|}

=== UART0 - J17 ===

J17 is a standard DB9 connector for the RS232 two-wires UART0 port. The following table reports the connector's pinout:

{| class="wikitable"

|-

!Pin#

!Pin name

!Function

!Notes

|-

|1, 6, 4, 9

|N.C.

|Connected to protection diode array

|-

|2

|ZYNQ_UART1_RX

|Receive line

|

|-

|3

|ZYNQ_UART1_TX

|Transmit line

|

|-

|5

|DGND

|Ground

|

|-

|7, 8

|N.C.

|Connected to protection diode array

|-

|}

=== Ethernet port ETH0 - J8 ===

J8 is a RJ45 Gigabit Ethernet connector connected to the Bora integrated ethernet controller and PHY.

{| class="wikitable"

|-

!Pin#

!Pin name

!Function

!Notes

|-

|1 || ETH_TXRX0_P || - || -

|-

|2 || ETH_TXRX0_M || - || -

|-

|3 || ETH_TXRX1_P || - || -

|-

|4 || ETH_TXRX2_P || - || -

|-

|5 || ETH_TXRX2_M || - || -

|-

|6 || ETH_TXRX1_M || - || -

|-

|7 || ETH_TXRX3_P || - || -

|-

|8 || ETH_TXRX3_M || - || -

|-

|9 || +3.3V || - || -

|-

|10 || ETH_SH || - || -

|-

|11, 13 || +3.3V || - || -

|-

|12 || 3.3V_ETH0_LED1 || - || -

|-

|14 || 3.3V_ETH0_LED2 || - || -

|-

|}

=== Pin strip connectors ===

==== JP2 ====

JP2 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:

{| class="wikitable"

==== JP3 ====

JP3 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:

{| class="wikitable"

==== JP4 ====

JP4 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:

{| class="wikitable"

==== JP5 ====

JP5 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:

{| class="wikitable"

==== JP6 ====

JP6 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:

{| class="wikitable"

==== JP7 ====

JP7 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:

{| class="wikitable"

==== JP8 ====

JP8 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:

{| class="wikitable"

==== JP9 ====

JP9 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:

{| class="wikitable"

==== JP10 ====

JP10 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:

{| class="wikitable"

==== JP11 ====

JP11 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:

{| class="wikitable"

==== JP13 ====

JP13 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:

{| class="wikitable"

==== JP14 ====

JP14 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:

{| class="wikitable"

==== JP15 ====

JP15 is a 12-pin 6x2x2.00 pitch vertical header. The following table reports the connector's pinout:

{| class="wikitable"

!Notes

|-

|1~~, 10, 11, 16~~ || ~~DGND~~ MON_VCCPLL || ~~Ground~~ - || -

|-

|2 || ~~xxx~~ MON_3.3V || - || -

|-

|3 || ~~xxx~~ MON_XADC_VCC || - || -

|-

|4 || ~~xxx~~ MON_1V2_ETH || - || -

|-

|5 || ~~xxx~~ MON_FPGA_VDDIO_BANK35 || - || -

|-

|6 || ~~xxx~~ MON_VDDQ_1V5 || - || -

|-

|7 || ~~xxx~~ MON_FPGA_VDDIO_BANK34 || - || -

|-

|8 || ~~xxx~~ MON_1.8V || - || -

|-

|9 || ~~xxx~~ MON_FPGA_VDDIO_BANK13 || - || -

|-

|10 || ~~xxx~~ MON_1.0V || - || -

|-

|11 || ~~xxx~~ MON_1.8V_IO || - || -

|-

|12 || ~~xxx~~ DGND || ~~- || -~~|-~~|13 || xxx || - || -~~|-~~|14 || xxx || - || -~~|-~~|15 || xxx || - || -~~|-~~|16 || xxx || -~~ Ground || -

|-

|}

==== JP16 ====

JP16 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:

{| class="wikitable"

==Schematics==

* ORCAD: ~~coming soon~~https://www.dave.eu/system/files/area-riservata/boraevb-lite-1.1.1-dsn.zip* PDF: ~~coming soon~~https://www.dave.eu/system/files/area-riservata/boraevb-lite_S.EVBB0000I0R_1.1.1_color.pdf

==BOM==

* ~~Coming soon~~ ~~==Layout==~~* Coming soon ~~==Mechanical==~~* DXFBoraEVB-Lite: ~~coming soon~~* IDF (3D)https: ~~coming soon~~//www.dave.eu/system/files/area-riservata/boraevb-lite_BOM_S%20EVBB0000I0R%201.1.1.CSV_.zip

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