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BoraEVB-Lite

2,807 bytes added, 12:28, 17 October 2018
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{{WorkInProgress}}{{InfoBoxTop}}{{Applies To Bora}}{{InfoBoxBottom}} {{WarningMessage|text=The information here This carrier board is '''obsolete''' and its shipment is discontinued. Starting from version 2.0.0 of the BELK, the official carrier board provided are preliminary and subject to changewith the BELK is the [[BoraEVB]].This wiki page remains published as reference, but won't be updated anymore}}
== Connectors pinout ==
 
=== Power supply - J7 ===
 
Power is provided through the J7 connector.
 
{| class="wikitable"
|-
!Pin#
!Pin name
!Function
!Notes
|-
|1 || VIN || Power supply || Nominal: +12V
|-
|2 || DGND || Ground || -
|-
|}
 
=== UART0 - J17 ===
 
J17 is a standard DB9 connector for the RS232 two-wires UART0 port. The following table reports the connector's pinout:
 
{| class="wikitable"
|-
!Pin#
!Pin name
!Function
!Notes
|-
|1, 6, 4, 9
|N.C.
|N.C.
|Connected to protection diode array
|-
|2
|ZYNQ_UART1_RX
|Receive line
|
|-
|3
|ZYNQ_UART1_TX
|Transmit line
|
|-
|5
|DGND
|Ground
|
|-
|7, 8
|N.C.
|N.C.
|Connected to protection diode array
|-
|}
 
 
=== Ethernet port ETH0 - J8 ===
 
J8 is a RJ45 Gigabit Ethernet connector connected to the Bora integrated ethernet controller and PHY.
 
{| class="wikitable"
|-
!Pin#
!Pin name
!Function
!Notes
|-
|1 || ETH_TXRX0_P || - || -
|-
|2 || ETH_TXRX0_M || - || -
|-
|3 || ETH_TXRX1_P || - || -
|-
|4 || ETH_TXRX2_P || - || -
|-
|5 || ETH_TXRX2_M || - || -
|-
|6 || ETH_TXRX1_M || - || -
|-
|7 || ETH_TXRX3_P || - || -
|-
|8 || ETH_TXRX3_M || - || -
|-
|9 || +3.3V || - || -
|-
|10 || ETH_SH || - || -
|-
|11, 13 || +3.3V || - || -
|-
|12 || 3.3V_ETH0_LED1 || - || -
|-
|14 || 3.3V_ETH0_LED2 || - || -
|-
|}
 
=== Pin strip connectors ===
==== JP2 ====
 
JP2 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:
{| class="wikitable"
==== JP3 ====
 
JP3 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:
{| class="wikitable"
==== JP4 ====
 
JP4 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:
{| class="wikitable"
|9 || IO_L20N_T3_34 || - || -
|-
|12 || N.A. ZYNQ_L6P_T0_34 || N.A. - || -Mount option
|-
|13 || IO_L1P_T0_34 || - || -
|}
==== JP5 ====
==== JP5 ====is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:
{| class="wikitable"
==== JP6 ====
 
JP6 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:
{| class="wikitable"
==== JP7 ====
 
JP7 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:
{| class="wikitable"
|2 || IO_L14P_T2_SRCC_34 || - || -
|-
|3 || N.A. ZYNQ_L10P_T1_34 || N.A. - || -Mount option
|-
|4 || IO_L14N_T2_SRCC_34 || - || -
|-
|5 || N.A. ZYNQ_L10N_T1_34 || N.A. - || -Mount option
|-
|7 || N.A. ZYNQ_25_34 || N.A. - || -Mount option
|-
|8 || IO_L11P_T1_SRCC_34 || - || -
|-
|9 || N.A. ZYNQ_0_34 || N.A. - || -Mount option
|-
|10 || IO_L11N_T1_SRCC_34 || - || -
==== JP8 ====
 
JP8 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:
{| class="wikitable"
==== JP9 ====
 
JP9 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:
{| class="wikitable"
==== JP10 ====
 
JP10 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:
{| class="wikitable"
|3, 6, 9, 12, 15 || XADC_GND || - || -
|-
|5 || ZYNQ_AD14P_35 || - || -Mount option
|-
|7 || ZYNQ_AD14N_35 || - || -Mount option
|-
|8 || ZYNQ_T0_VREF_35 || - || -Mount option
|-
|10 || ZYNQ_T3_VREF_35 || - || -Mount option
|-
|11 || ZYNQ_AD1P_35 || - || -Mount option
|-
|13 || ZYNQ_AD1N_35 || - || -Mount option
|-
|14 || ZYNQ_AD3P_35 || - || -Mount option
|-
|16 || ZYNQ_AD3N_35 || - || -Mount option
|-
|}
==== JP11 ====
 
JP11 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:
{| class="wikitable"
!Notes
|-
|1, 10, 11, 16 7 || DGND XADC_AGND || Ground || -
|-
|2 || xxx SYS_RSTn || - || -
|-
|3 || xxx XADC_VN_R || - || -
|-
|4 || xxx PORSTn || - || -
|-
|5 || xxx XADC_VP_R || - || -
|-
|6 || xxx MRSTn || - || -
|-
|7 8 || xxx 1.0V_ENA || - || -
|-
|8 9 || xxx FPGA_INIT_B || - || -
|-
|9 10, 15 || xxx DGND || - Ground || -
|-
|10 11 || xxx FPGA_PROGRAM_B || - || -
|-
|11 12 || xxx WD_SET0 || - || -
|-
|12 13 || xxx FPGA_DONE || - || -
|-
|13 14 || xxx WD_SET1 || - || -
|-
|14 || xxx || - || -|-|15 || xxx || - || -|-|16 || xxx WD_SET2 || - || -
|-
|}
==== JP12 ====
{| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|1, 10, 11, 16 || DGND || Ground || -|-|2 || xxx || - || - |-|3 || xxx || - || -|-|4 || xxx || - || -|-|5 || xxx || - || -|-|6 || xxx || - || -|-|7 || xxx || - || -|-|8 || xxx || - || -|-|9 || xxx || - || -|-|10 || xxx || - || -|-|11 || xxx || - || -|-|12 || xxx || - || -|-|13 || xxx || - || -|-|14 || xxx || - || -|-|15 || xxx || - || -|-|16 || xxx || - || -|-|}=== JP13 ====
==== JP13 ====is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:
{| class="wikitable"
!Notes
|-
|1, 104, 119, 16 12 || DGND || Ground || -|-|2 || xxx || - || - |-|3 || xxx || - || -|-|4 || xxx || - || -
|-
|5 2 || xxx SPI0_CS0n || - || -
|-
|6 3 || xxx ZYNQ_SPI0_SCLK/NAND_IO1 || - || -
|-
|7 5 || xxx ZYNQ_SPI0_DQ0/NAND_ALE || - || -
|-
|8 6 || xxx NAND_CS0/SPI0_CS1 || - || -
|-
|9 7 || xxx ZYNQ_SPI0_DQ2/NAND_IO2 || - || -
|-
|10 8 || xxx ZYNQ_SPI0_DQ1/NAND_WE || - || -
|-
|11 10 || xxx ZYNQ_SPI0_DQ3/NAND_IO0 || - || -
|-
|12 11 || xxx ZYNQ_NAND_RD_B || - || -
|-
|13 || xxx ZYNQ_NAND_CLE || - || -
|-
|14 || xxx NAND_BUSY || - || -
|-
|15 || xxx NAND_IO4 || - || -
|-
|16 || xxx NAND_IO3 || - || -
|-
|}
==== JP14 ====
 
JP14 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:
{| class="wikitable"
!Notes
|-
|1, 10, 11, 16 || DGND NAND_IO6 || Ground - || -
|-
|2 || xxx NAND_IO5 || - || -
|-
|3 , 9 || xxx DGND || - Ground || -
|-
|4 || xxx NAND_IO7 || - || -
|-
|5 || xxx CLK125_NDO || - || -
|-
|6 || xxx MEM_WPn || - || -
|-
|7 || xxx ETH1_CLK125_NDO || - || -
|-
|8 || xxx ETH_INTn || - || -
|-
|9 10 || xxx ETH1_INTn || - || -
|-
|10 11 || xxx INA_ALERT || - || -
|-
|11 12 || xxx ETH1_RESETn || - || -
|-
|12 13 || xxx RTC_INT/SQW || - || -
|-
|13 14 || xxx IO_ETH0_RESETn || - || -
|-
|14 15 || xxx PS_MIO15_500 || - || -
|-
|15 || xxx || - || -|-|16 || xxx IO_OTG_RESETn || - || -
|-
|}
==== JP15 ====
 
JP15 is a 12-pin 6x2x2.00 pitch vertical header. The following table reports the connector's pinout:
{| class="wikitable"
!Notes
|-
|1, 10, 11, 16 || DGND || Ground || -|-|2 || xxx || - || - |-|3 || xxx || - || -|-|4 || xxx MON_VCCPLL || - || -
|-
|5 2 || xxx MON_3.3V || - || -
|-
|6 3 || xxx MON_XADC_VCC || - || -
|-
|7 4 || xxx MON_1V2_ETH || - || -
|-
|8 5 || xxx MON_FPGA_VDDIO_BANK35 || - || -
|-
|9 6 || xxx MON_VDDQ_1V5 || - || -
|-
|10 7 || xxx MON_FPGA_VDDIO_BANK34 || - || -
|-
|11 8 || xxx MON_1.8V || - || -
|-
|12 9 || xxx MON_FPGA_VDDIO_BANK13 || - || -
|-
|13 10 || xxx MON_1.0V || - || -
|-
|14 11 || xxx MON_1.8V_IO || - || -
|-
|15 12 || xxx DGND || - || -|-|16 || xxx || - Ground || -
|-
|}
==== JP16 ====
 
JP16 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:
{| class="wikitable"
==Schematics==
* ORCAD: coming soonhttps://www.dave.eu/system/files/area-riservata/boraevb-lite-1.1.1-dsn.zip* PDF: coming soonhttps://www.dave.eu/system/files/area-riservata/boraevb-lite_S.EVBB0000I0R_1.1.1_color.pdf
==BOM==
* Coming soon ==Layout==* Coming soon ==Mechanical==* DXFBoraEVB-Lite: coming soon* IDF (3D)https: coming soon//www.dave.eu/system/files/area-riservata/boraevb-lite_BOM_S%20EVBB0000I0R%201.1.1.CSV_.zip
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