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BoraEVB-Lite

6,012 bytes added, 12:28, 17 October 2018
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{{WorkInProgress}}{{InfoBoxTop}}{{Applies To Bora}}{{InfoBoxBottom}} {{WarningMessage|text=The information here This carrier board is '''obsolete''' and its shipment is discontinued. Starting from version 2.0.0 of the BELK, the official carrier board provided are preliminary and subject to changewith the BELK is the [[BoraEVB]].This wiki page remains published as reference, but won't be updated anymore}}
== Connectors pinout ==
 
=== Power supply - J7 ===
 
Power is provided through the J7 connector.
 
{| class="wikitable"
|-
!Pin#
!Pin name
!Function
!Notes
|-
|1 || VIN || Power supply || Nominal: +12V
|-
|2 || DGND || Ground || -
|-
|}
 
=== UART0 - J17 ===
 
J17 is a standard DB9 connector for the RS232 two-wires UART0 port. The following table reports the connector's pinout:
 
{| class="wikitable"
|-
!Pin#
!Pin name
!Function
!Notes
|-
|1, 6, 4, 9
|N.C.
|N.C.
|Connected to protection diode array
|-
|2
|ZYNQ_UART1_RX
|Receive line
|
|-
|3
|ZYNQ_UART1_TX
|Transmit line
|
|-
|5
|DGND
|Ground
|
|-
|7, 8
|N.C.
|N.C.
|Connected to protection diode array
|-
|}
 
 
=== Ethernet port ETH0 - J8 ===
 
J8 is a RJ45 Gigabit Ethernet connector connected to the Bora integrated ethernet controller and PHY.
 
{| class="wikitable"
|-
!Pin#
!Pin name
!Function
!Notes
|-
|1 || ETH_TXRX0_P || - || -
|-
|2 || ETH_TXRX0_M || - || -
|-
|3 || ETH_TXRX1_P || - || -
|-
|4 || ETH_TXRX2_P || - || -
|-
|5 || ETH_TXRX2_M || - || -
|-
|6 || ETH_TXRX1_M || - || -
|-
|7 || ETH_TXRX3_P || - || -
|-
|8 || ETH_TXRX3_M || - || -
|-
|9 || +3.3V || - || -
|-
|10 || ETH_SH || - || -
|-
|11, 13 || +3.3V || - || -
|-
|12 || 3.3V_ETH0_LED1 || - || -
|-
|14 || 3.3V_ETH0_LED2 || - || -
|-
|}
 
=== Pin strip connectors ===
==== JP2 ====
 
JP2 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:
{| class="wikitable"
|1, 10, 11, 16 || DGND || Ground || -
|-
|2 || IO_L19P_T3_34 ZYNQ_L19P_T3_34 || - || -Mount option
|-
|3 || IO_L2P_T0_34 || - || -
==== JP3 ====
 
JP3 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:
{| class="wikitable"
==== JP4 ====
 
JP4 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:
{| class="wikitable"
|9 || IO_L20N_T3_34 || - || -
|-
|12 || N.A. ZYNQ_L6P_T0_34 || N.A. - || -Mount option
|-
|13 || IO_L1P_T0_34 || - || -
|}
==== JP5 ====
==== JP5 ====is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:
{| class="wikitable"
==== JP6 ====
 
JP6 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:
{| class="wikitable"
|1, 10, 11, 16 || DGND || Ground || -
|-
|2 || xxx IO_L16P_T2_13 || - || - |-|3 || IO_L20P_T3_13 || - || -|-|4 || IO_L16N_T2_13 || - || -|-|5 || IO_L20N_T3_13 || - || -|-|6 || IO_L22P_T3_13 || - || -|-|7 || IO_L17P_T2_13 || - || -|-|8 || IO_L22N_T3_13 || - || -|-|9 || IO_L17N_T2_13 || - || -|-|12, 14 || VDDIO_BANK13 || - || -|-|13 || IO_L19P_T3_13 || - || -
|-
|3 15 || xxx IO_L19N_T3_VREF_13 || - || -|-|} ==== JP7 ==== JP7 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout: {| class="wikitable"
|-
|4 || xxx || - || -!Pin# !Pin name!Function!Notes
|-
|5 1, 6, 11, 12 || xxx DGND || - Ground || -
|-
|6 2 || xxx IO_L14P_T2_SRCC_34 || - || -
|-
|7 3 || xxx ZYNQ_L10P_T1_34 || - || -Mount option
|-
|8 4 || xxx IO_L14N_T2_SRCC_34 || - || -
|-
|9 5 || xxx ZYNQ_L10N_T1_34 || - || -Mount option
|-
|10 7 || xxx ZYNQ_25_34 || - || -Mount option
|-
|11 8 || xxx IO_L11P_T1_SRCC_34 || - || -
|-
|12 9 || xxx ZYNQ_0_34 || - || -Mount option
|-
|13 10 || xxx IO_L11N_T1_SRCC_34 || - || -
|-
|14 13 || xxx IO_L3P_T0_DQS_PUDC_B_34 || - || -
|-
|15 14, 16 || xxx N.C. || - Not connected || -
|-
|16 15 || xxx IO_L3N_T0_DQS_34 || - || -
|-
|}
==== JP7 JP8 ==== JP8 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout: {| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|1, 7, 10, 13, 16 || DGND || Ground || -|-|2 || IO_L21P_T3_DQS_13 || - || - |-|3 || IO_L15P_T2_DQS_13 || - || -|-|4 || IO_L21N_T3_DQS_13 || - || -|-|5 || IO_L15N_T2_DQS_13 || - || -|-|6 || IO_L18P_T2_13 || - || -|-|8 || IO_L18N_T2_13 || - || -|-|9 || IO_L11P_T1_SRCC_13 || - || -|-|11 || IO_L11N_T1_SRCC_13 || - || -|-|12 || IO_L13P_T2_MRCC_13 || - || -|-|14 || IO_L13N_T2_MRCC_13 || - || -|-|15 || VDDIO_BANK13 || - || -|-|} ==== JP9 ==== JP9 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout: {| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|1, 7, 13 || DGND || Ground || -|-|2, 4, 6, 8, 10<br>12, 14, 15, 16 || N.C. || Not connected || - |-|3 || IO_L12P_T1_MRCC_34 || - || -|-|5 || IO_L12N_T1_MRCC_34 || - || -|-|9 || IO_L13P_T2_MRCC_34 || - || -|-|11 || IO_L13N_T2_MRCC_34 || - || -|-|} ==== JP10 ==== JP10 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:
{| class="wikitable"
!Notes
|-
|1|| IO_0_35 || - || -|-|2, 4 || VDDIO_BANK35 || - || - |-|3, 6, 9, 12, 15 || XADC_GND || - || -|-|5 || ZYNQ_AD14P_35 || - || Mount option|-|7 || ZYNQ_AD14N_35 || - || Mount option|-|8 || ZYNQ_T0_VREF_35 || - || Mount option|-|10, || ZYNQ_T3_VREF_35 || - || Mount option|-|11, || ZYNQ_AD1P_35 || - || Mount option|-|13 || ZYNQ_AD1N_35 || - || Mount option|-|14 || ZYNQ_AD3P_35 || - || Mount option|-|16 || DGND ZYNQ_AD3N_35 ||- | Ground |Mount option| -|} ==== JP11 ==== JP11 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout: {| class="wikitable"
|-
|2 || xxx || - || - !Pin# !Pin name!Function!Notes
|-
|3 1, 7 || xxx XADC_AGND || - Ground || -
|-
|4 2 || xxx SYS_RSTn || - || -
|-
|5 3 || xxx XADC_VN_R || - || -
|-
|6 4 || xxx PORSTn || - || -
|-
|7 5 || xxx XADC_VP_R || - || -
|-
|8 6 || xxx MRSTn || - || -
|-
|9 8 || xxx 1.0V_ENA || - || -
|-
|10 9 || xxx FPGA_INIT_B || - || -
|-
|11 10, 15 || xxx DGND || - Ground || -
|-
|12 11 || xxx FPGA_PROGRAM_B || - || -
|-
|13 12 || xxx WD_SET0 || - || -
|-
|14 13 || xxx FPGA_DONE || - || -
|-
|15 14 || xxx WD_SET1 || - || -
|-
|16 || xxx WD_SET2 || - || -
|-
|}
==== JP8 JP13 ==== JP13 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout:
{| class="wikitable"
!Notes
|-
|1, 104, 119, 16 12 || DGND || Ground || -|-|2 || SPI0_CS0n || - || - |-|3 || ZYNQ_SPI0_SCLK/NAND_IO1 || - || -|-|5 || ZYNQ_SPI0_DQ0/NAND_ALE || - || -|-|6 || NAND_CS0/SPI0_CS1 || - || -|-|7 || ZYNQ_SPI0_DQ2/NAND_IO2 || - || -|-|8 || ZYNQ_SPI0_DQ1/NAND_WE || - || -|-|10 || ZYNQ_SPI0_DQ3/NAND_IO0 || - || -|-|11 || ZYNQ_NAND_RD_B || - || -|-|13 || ZYNQ_NAND_CLE || - || -|-|14 || NAND_BUSY || - || -|-|15 || NAND_IO4 || - || -|-|16 || NAND_IO3 || - || -|-|} ==== JP14 ==== JP14 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout: {| class="wikitable" |-!Pin# !Pin name!Function!Notes
|-
|2 1 || xxx NAND_IO6 || - || -
|-
|3 2 || xxx NAND_IO5 || - || -
|-
|4 3, 9 || xxx DGND || - Ground || -
|-
|5 4 || xxx NAND_IO7 || - || -
|-
|6 5 || xxx CLK125_NDO || - || -
|-
|7 6 || xxx MEM_WPn || - || -
|-
|8 7 || xxx ETH1_CLK125_NDO || - || -
|-
|9 8 || xxx ETH_INTn || - || -
|-
|10 || xxx ETH1_INTn || - || -
|-
|11 || xxx INA_ALERT || - || -
|-
|12 || xxx ETH1_RESETn || - || -
|-
|13 || xxx RTC_INT/SQW || - || -
|-
|14 || xxx IO_ETH0_RESETn || - || -
|-
|15 || xxx PS_MIO15_500 || - || -
|-
|16 || xxx IO_OTG_RESETn || - || -
|-
|}
==== JP9 JP15 ==== JP15 is a 12-pin 6x2x2.00 pitch vertical header. The following table reports the connector's pinout:
{| class="wikitable"
!Notes
|-
|1, 10, 11, 16 || DGND MON_VCCPLL || Ground - || -|-|2 || MON_3.3V || - || - |-|3 || MON_XADC_VCC || - || -|-|4 || MON_1V2_ETH || - || -|-|5 || MON_FPGA_VDDIO_BANK35 || - || -|-|6 || MON_VDDQ_1V5 || - || -|-|7 || MON_FPGA_VDDIO_BANK34 || - || -
|-
|2 8 || xxx MON_1.8V || - || -
|-
|3 9 || xxx MON_FPGA_VDDIO_BANK13 || - || -
|-
|4 10 || xxx MON_1.0V || - || -
|-
|5 11 || xxx MON_1.8V_IO || - || -
|-
|6 12 || xxx DGND || - Ground || -
|-
|7 || xxx || } ==== JP16 ==== JP16 is a 16- pin 8x2x2.54 pitch vertical header. The following table reports the connector's pinout: {|| -class="wikitable"
|-
|8 || xxx || - || -!Pin# !Pin name!Function!Notes
|-
|9 1 || xxx VDDIO_BANK13 || - || -
|-
|10 2, 4, 7, 13, 14 || xxx || - || -
|-
|11 3 || xxx IO_L14P_T2_SRCC_13 || - || -
|-
|12 5 || xxx IO_L14N_T2_SRCC_13 || - || -
|-
|13 6 || xxx ZYNQ_L6N_T0_VREF_13 || - || -
|-
|14 8, 10, 12, 15, 16 || xxx DGND || - Ground || -
|-
|15 9 || xxx IO_L12P_T1_MRCC_13 || - || -
|-
|16 11 || xxx IO_L12N_T1_MRCC_13 || - || -
|-
|}
==Schematics==
* ORCAD: coming soonhttps://www.dave.eu/system/files/area-riservata/boraevb-lite-1.1.1-dsn.zip* PDF: coming soonhttps://www.dave.eu/system/files/area-riservata/boraevb-lite_S.EVBB0000I0R_1.1.1_color.pdf
==BOM==
* Coming soon ==Layout==* Coming soon ==Mechanical==* DXFBoraEVB-Lite: coming soon* IDF (3D)https: coming soon//www.dave.eu/system/files/area-riservata/boraevb-lite_BOM_S%20EVBB0000I0R%201.1.1.CSV_.zip
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