Bureaucrats, dave_user, Administrators
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Created page with "<section begin=History/> {| style="border-collapse:collapse; " !colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History |- !style="border-le..."
<section begin=History/>
{| style="border-collapse:collapse; "
!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History
|-
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes
|-
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|2024/02/13
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|First documentation release
|}
<section end=History/>
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<section begin=Body/>
==LVDS ==
=== Description ===
SBCX provides two LVDS interfaces, LVDS0 and LVDS1. AURA SOM supports one LVDS channel on J8 Hirose (cod. DF13A-20DP-1.25V) double row 1.25mm pitch miniature crimping connector.
[[File:AXEL Lite-EVB-LVDS-connector.png|thumb|center| 500px|LVDS connectors]]
===Signals ===
The following tables describes the interface signals
==== LVDS0 ====
{| class="wikitable"
! latexfontsize="scriptsize"| Pin#
! latexfontsize="scriptsize"| SOM Pin#
! latexfontsize="scriptsize"| Pin name
! latexfontsize="scriptsize"| Pin function
! latexfontsize="scriptsize"| Pin Notes
|-
| 1, 2 || - || 3.3V_LCD0 || 3.3 V||
|-
| 3, 4, 7, 10,
13, 16, 19
| - || DGND || Ground||
|-
| 5 || J10.137 || LVDS0_TX0_N || LVDS Data 0 -||
|-
| 6 || J10.139 || LVDS0_TX0_P || LVDS Data 0 +||
|-
| 8 || J10.141 || LVDS0_TX1_N || LVDS Data 1 -||
|-
| 9 || J10.143 || LVDS0_TX1_P || LVDS Data 1 +||
|-
| 11 || J10.145 || LVDS0_TX2_N || LVDS Data 2 -||
|-
| 12 || J10.147 || LVDS0_TX2_P || LVDS Data 2 +||
|-
| 14 || J10.133 || LVDS0_CLK_N || LVDS Clock -||
|-
| 15 || J10.135 || LVDS0_CLK_P || LVDS Clock +||
|-
| 17 || J10.149 || LVDS0_P17 || LVDS_TX3_N ||
|-
| 18 || J10.151 || LVDS0_P18 || LVDS_TX3_P ||
|-
| 20 || J10.46 || LVDS0_P20 || TPM3.CH3 ||
|}
=== Device mapping ===
LVDS is mapped to <code>LVDS-1</code> DRM ''"connector"'': see [[DESK-MX9-L/Peripherals/LVDS | DESK-MX9-L LVDS]] peripheral.
=== Power sequence ===
Most of the LCD panels have many supplies and need a specific timing to power the rails and start the signals.
The Evaluation Kit provides GPIO controlled power rails that can be leveraged both at bootloader and kernel level to meet any specifications.
The following sections describe the available rails:
==== 3V3_LCD ====
The most common voltage to supply the LCD panel internal rail 3V3_LCD0 is enabled by <code>GPIO1_IO10 </code>
==== 5V_LCD ====
The most common voltage to supply the LCD panel backlight rail 5V_LCD0 is enabled by <code>GPIO2_IO24</code>
=== Device usage ===
The associated framebuffer device is accessed in Linux through the standard graphic access.
<section begin=Body/>
[[Category:AURA]]
{| style="border-collapse:collapse; "
!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History
|-
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes
|-
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|2024/02/13
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|First documentation release
|}
<section end=History/>
__FORCETOC__
<section begin=Body/>
==LVDS ==
=== Description ===
SBCX provides two LVDS interfaces, LVDS0 and LVDS1. AURA SOM supports one LVDS channel on J8 Hirose (cod. DF13A-20DP-1.25V) double row 1.25mm pitch miniature crimping connector.
[[File:AXEL Lite-EVB-LVDS-connector.png|thumb|center| 500px|LVDS connectors]]
===Signals ===
The following tables describes the interface signals
==== LVDS0 ====
{| class="wikitable"
! latexfontsize="scriptsize"| Pin#
! latexfontsize="scriptsize"| SOM Pin#
! latexfontsize="scriptsize"| Pin name
! latexfontsize="scriptsize"| Pin function
! latexfontsize="scriptsize"| Pin Notes
|-
| 1, 2 || - || 3.3V_LCD0 || 3.3 V||
|-
| 3, 4, 7, 10,
13, 16, 19
| - || DGND || Ground||
|-
| 5 || J10.137 || LVDS0_TX0_N || LVDS Data 0 -||
|-
| 6 || J10.139 || LVDS0_TX0_P || LVDS Data 0 +||
|-
| 8 || J10.141 || LVDS0_TX1_N || LVDS Data 1 -||
|-
| 9 || J10.143 || LVDS0_TX1_P || LVDS Data 1 +||
|-
| 11 || J10.145 || LVDS0_TX2_N || LVDS Data 2 -||
|-
| 12 || J10.147 || LVDS0_TX2_P || LVDS Data 2 +||
|-
| 14 || J10.133 || LVDS0_CLK_N || LVDS Clock -||
|-
| 15 || J10.135 || LVDS0_CLK_P || LVDS Clock +||
|-
| 17 || J10.149 || LVDS0_P17 || LVDS_TX3_N ||
|-
| 18 || J10.151 || LVDS0_P18 || LVDS_TX3_P ||
|-
| 20 || J10.46 || LVDS0_P20 || TPM3.CH3 ||
|}
=== Device mapping ===
LVDS is mapped to <code>LVDS-1</code> DRM ''"connector"'': see [[DESK-MX9-L/Peripherals/LVDS | DESK-MX9-L LVDS]] peripheral.
=== Power sequence ===
Most of the LCD panels have many supplies and need a specific timing to power the rails and start the signals.
The Evaluation Kit provides GPIO controlled power rails that can be leveraged both at bootloader and kernel level to meet any specifications.
The following sections describe the available rails:
==== 3V3_LCD ====
The most common voltage to supply the LCD panel internal rail 3V3_LCD0 is enabled by <code>GPIO1_IO10 </code>
==== 5V_LCD ====
The most common voltage to supply the LCD panel backlight rail 5V_LCD0 is enabled by <code>GPIO2_IO24</code>
=== Device usage ===
The associated framebuffer device is accessed in Linux through the standard graphic access.
<section begin=Body/>
[[Category:AURA]]