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AURA SOM/AURA Hardware/Power and Reset/System boot

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This page illustrates the characteristics of the AURA's boot subsystem[[File:TBD. Reading of the chapter ''System Boot'' of the ''i.MX 93 Applications Processor Reference Manual'' is highly recommended [1png | center | 400px]], though. i.MX93 SOC features several options in terms of booting. Such options are detailed in that document.
It is worth remembering that, by default, AURA supports ''Single Boot'' modes, i.e. the Cortex-A55 is the boot core. Other options are available on-demand, however, allowing to implement other configurations. DAVE Embedded Systems' team is available for additional information on this matter. If necessary, please contact [mailto:sales@dave.eu sales@dave.eu].<section end="History" />__FORCETOC__<section begin="Body" />
== System boot ==
The boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM Cortex-A55 core to begin execution starting from the on-chip boot ROM. The boot ROM:
* determines whether the boot is secure or non-secure
* performs some initialization of the system and clean-ups
=== Boot options ===
The default primary Two options are available related to system boot device is defined at the factory and . They are identified by the 'Boot Mode' field of the ordering code as follows:
* 0: SPI NOR / SD option (SOM code: DAUxxx0xxxxR)
* 1: eMMC / SD option (SOM code: DAUxxx1xxxxRDAUxxx2xxxxR)* 2: SPI NAND / SD option (SOM code: DAUxxx2xxxxRDAUxxx1xxxxR)For both options an alternative the selection of primary boot from SD/MMC card device is provided, selectable determined by driving low the BOOT_MODE_SEL signalas described in the following sections. Bootable SD/MMC card connects via the SD2 (USDHC2) busBOOT_MODE_SEL is latched when processor reset is released.
All boot modes provide 'single boot' mode, meaning that the Cortex-A55 is the first core to boot. In any case, boot process is managed by on-chip boot ROM code that is described in detail in processor's Reference Manual.{| class==== SPI NOR / SD option ===="wikitable"!Ordering code 'Boot Mode' fileld!BOOT_MODE_SEL!Primary Selection of primary boot deviceis determined by the BOOT_MODE_SEL signal as follows:|-| rowspan* BOOT_MODE_SEL ="2" |0|0** primary boot device is SD2 (USDHC2)|* boot ROM will try to boot a valid image from the SD/MMC card on USDHC2|-|1|FlexSPI first, and then from the SPI NOR on FLEXSPI1. In case no valid image is found, boot ROM shall enable USB serial download mode automatically|-| rowspan* BOOT_MODE_SEL ="2" |1or floating|0** primary boot device is SPI NOR flash connected to FLEXSPI|SD/MMC card on USDHC2|-|1|eMMC on USDHC1|-| rowspan="2" |2|0|SD/MMC card on USDHC2|-|1|FlexSPI NAND on FLEXSPI1|}** in case no valid image is found in SPI NOR flash, boot ROM shall enable USB serial download mode automatically
=== Note on boot signals = eMMC / SD option ====Selection of primary boot device is determined by the BOOT_MODE_SEL signal as follows:* BOOT_MODE_SEL = 0** primary boot device is latched when processor reset CPU_PORn SD2 (USDHC2)** in case no valid image is released. Inside the SOMfound in SD card, boot ROM shall enable USB serial download mode automatically * BOOT_MODE_SEL is pulled-up with 10 kohm.= 1 or floating* The iMX93x SoC uses some GPIOs to read the * primary boot configuration set on the SOM: for this reason the SOM's ports UART1_TXD, UART2_TXD, SAI1_TXFS and SAI1_TXD0 are floating (high impedance) while CPU_PORn signal device is low.eMMC connected to USDHC1[[File:AURA-** in case no valid image is found in eMMC flash, boot-opt.png | 800px]]ROM shall enable USB serial download mode automatically
=== Note on boot = SPI NAND / SD option ====Selection of primary boot device is determined by the BOOT_MODE_SEL signal as follows:* BOOT_MODE_SEL =0** primary boot device is SD2 (USDHC2)In ** in case no valid image is found in SD card, boot ROM shall enable USB serial download mode automatically * BOOT_MODE_SEL = 1 or floating** primary boot deviceis SPI NAND flash connected to FLEXSPI** in case no valid image is found in SPI NAND flash, boot ROM shall enable USB serial download mode automatically on USB OTG1.
===Important note for ''manufacture mode'' management===
Bootstrap stage has to be intended as the time elapsing between the release of hardware reset (CPU_PORn) and the execution of the first instruction of user code (typically this is the reset vector of U-Boot boot loader).
== References ==[1] NXP, i.MX 93 Applications Processor Reference Manual <section end="Body" />
[[Category:AURA]]
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