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! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History

! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes

| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |2024/02/dd| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First documentation release

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The default primary Two options are available related to system boot device is defined at the factory and . They are identified by the 'Boot Mode' fileld field of the ordering code as follows:

* 1: eMMC / SD option (SOM code: DAUxxx1xxxxRDAUxxx2xxxxR)* 2: SPI NAND / SD option (SOM code: DAUxxx2xxxxRDAUxxx1xxxxR)For both options an alternative the selection of primary boot from SD/MMC card device is provided, selectable determined by driving low the BOOT_MODE_SEL signalas described in the following sections. Bootable SD/MMC card connects via the SD2 (USDHC2) busBOOT_MODE_SEL is latched when processor reset is released.

All boot modes provide 'single boot' mode, meaning that the Cortex-A55 is the first core to boot. In any case, boot process is managed by on-chip boot ROM code that is described in detail in processor's Reference Manual.{| class==== SPI NOR / SD option ===="wikitable"!Ordering code 'Boot Mode' fileld!BOOT_MODE_SEL!Primary Selection of primary boot deviceis determined by the BOOT_MODE_SEL signal as follows:|-| rowspan* BOOT_MODE_SEL ="2" |0|0** primary boot device is SD2 (USDHC2)|* boot ROM will try to boot a valid image from the SD/MMC card on USDHC2|-|1|FlexSPI first, and then from the SPI NOR on FLEXSPI1. In case no valid image is found, boot ROM shall enable USB serial download mode automatically|-| rowspan* BOOT_MODE_SEL ="2" |1or floating|0** primary boot device is SPI NOR flash connected to FLEXSPI|SD/MMC card on USDHC2|-|1|eMMC on USDHC1|-| rowspan="2" |2|0|SD/MMC card on USDHC2|-|1|FlexSPI NAND on FLEXSPI1|}Other options are available on-demand, however. DAVE Embedded Systems' team ** in case no valid image is available for additional information on this matter. If necessaryfound in SPI NOR flash, please contact [mailto:sales@dave.eu sales@dave.eu].boot ROM shall enable USB serial download mode automatically

=== Note on boot signals = eMMC / SD option ====Selection of primary boot device is determined by the BOOT_MODE_SEL signal as follows:* BOOT_MODE_SEL = 0** primary boot device is latched when processor reset CPU_PORn SD2 (USDHC2)** in case no valid image is released. Inside the SOMfound in SD card, boot ROM shall enable USB serial download mode automatically * BOOT_MODE_SEL is pulled-up with 10 kohm.= 1 or floating* The iMX93x SoC uses some GPIOs to read the * primary boot configuration set on the SOM: for this reason the SOM's ports UART1_TXD, UART2_TXD, SAI1_TXFS and SAI1_TXD0 are floating (high impedance) while CPU_PORn signal device is low.eMMC connected to USDHC1[[File:AURA-** in case no valid image is found in eMMC flash, boot-opt.png | 800px]]ROM shall enable USB serial download mode automatically

=== Note on boot = SPI NAND / SD option ====Selection of primary boot device is determined by the BOOT_MODE_SEL signal as follows:* BOOT_MODE_SEL =0** primary boot device is SD2 (USDHC2)In ** in case no valid image is found in SD card, boot ROM shall enable USB serial download mode automatically * BOOT_MODE_SEL = 1 or floating** primary boot deviceis SPI NAND flash connected to FLEXSPI** in case no valid image is found in SPI NAND flash, boot ROM shall enable USB serial download mode automatically on USB OTG1.

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