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<section begin="History" />
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|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|X.Y.Z2020/12/30|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Month Year|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|TBD|-|-|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|[TBD_link X.Y.Z]|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Month Year|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|TBD|-|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|...|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|...|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|...First version
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<section end="History" /><section begin="Body" /> ''TBD: nella pagina vanno documentate le varie sezioni e documentate ad hoc a seconda del SoC (ad esempio per Bora va aggiunta la sezione PL)''
== Processor and memory subsystem ==
The heart of ETRA module is composed by the following components:
* ''TBD: SOC name'' STM32MP1 SoC application processor
* Power supply unit
* DDR DDR3L memory banks
* NOR and NAND flash banks
* ''TBD: SOM connector type'' SODIMM-DDR3 form-factor and connector with interfaces signals
This chapter shortly describes the main Axel Lite ETRA components.
=== Processor Info ===
{| class="wikitable" |
| align="center" style="background:#f0f0f0;"|'''Processor'''| align="center" style="background:#f0f0f0;"|'''# Cores'''| align="center" style="background:#f0f0f0;"|'''Clock'''| align="center" style="background:#f0f0f0;"|'''L2 Cache'''| align="center" style="background:#f0f0f0;"|'''DDR3'''| align="center" style="background:#f0f0f0;"|'''Graphics AccelerationMCU'''| align="center" style="background:#f0f0f0;"|'''IPU'''| align="center" style="background:#f0f0f0;"|'''VPUGraphics Acceleration'''| align="center" style="background:#f0f0f0;"|'''SATA-IITemp grade'''
|-
| i.MX6 Solo STM32MP151 || 1 ||800 MHz650MHz<br>1 GHz 800 MHz ||512 256 KB ||16/32 bit @ 400 533 MHz ||3D: Vivante GC880<br>2D: Vivante GC320<br>Vector: N.A. ||1x 32 bit Arm Cortex M4 @209MHZ||1x ||N.A.-40 +125°C
|-
| i.MX6 Dual STM32MP153 || 2 ||850 MHz650MHz<br>1 GHz<br>1.2 GHz 800 MHz ||1 MB 256 KB ||64 16/32 bit @ 533 MHz ||3D: Vivante GC2000<br>2D: Vivante GC320<br>Vector: Vivante GC335 ||2x 32 bit Arm Cortex M4 @209MHZ||2x || Yes-40 +125°C
|-
| i.MX6 Quad STM32MP157 || 4 2 ||850 MHz650MHz<br>1 GHz<br>1.2 GHz 800 MHz ||1 MB 256 KB ||64 16/32 bit @ 533 MHz |32 bit Arm Cortex M4 @209MHZ||3D: Vivante GC2000GC Nano || -40 +125°C<br>2D: Vivante GC320<br>Vector: Vivante GC335 ||2x ||2x || Yes-20 +105°C
|-
|+ align="bottom" style="caption-side: bottom" | Table: i.MX6 STM32MP1 models comparison
|}
=== RAM memory bank ===
{| class="wikitable" |
| '''CPU connection'''||Multi-mode DDR controller (MMDC)
|-
| '''Size min'''||512 128 MB
|-
| '''Size max'''||4 1 GB
|-
| '''Width'''||64 16 bit
|-
| '''Speed'''||533 MHz
=== NOR flash bank ===
NOR flash is a Serial Peripheral Interface (SPI) device. This device is connected to the eCSPI QUADSPI channel 5 . and by default it acts can act as boot memory. The following table reports the NOR flash specifications:
{| class="wikitable" |
|-
| '''CPU connection'''||eCSPI channel 5QUADSPI
|-
| '''Size min'''||8 16 MB
|-
| '''Size max'''||64 32 MB
|-
| '''Chip select'''||ECSPI5_SS0PB6
|-
| '''Bootable'''||Yes
|-
|}
NOTE: the QUADSPI pins are shared with other interfaces. Make shure to not populate the other devices to use this peripheral.
=== NAND flash bank ===
On board main alternate storage memory is a 8-bit wide NAND flash connected to the CPU's Raw NAND flash controller. Optionally, it can act as boot peripheral. The following table reports the NAND flash specifications:
{| class="wikitable" |
| '''Width'''||8 bit
|-
| '''Chip select'''||NANDF_CS0PG9
|-
| '''Bootable'''||Yes
|-
|}
NOTE: the NAND pins are shared with other interfaces. Make shure to not populate the other devices to use this peripheral.
=== eMMC flash bank ===
On board main storage memory is a 8-bit wide eMMC device connected to SDMMC2 controller and by default it acts as boot peripheral. The following table reports the eMMC flash specifications:
{| class="wikitable" |
|-
| '''CPU connection'''|| SDIO|-| '''Page size'''|| xxxxxx SDMMC2
|-
| '''Size min'''||xxx MB 4 GB
|-
| '''Size max'''||xxx 8 GB
|-
| '''Width'''|| xx 4/8 bit
|-
| '''SDHC'''||No
|-
| '''Bootable'''||Yes
|-
|}
NOTE: the SDMMC2 pins are shared with other interfaces. Make shure to not populate the other devices to use this peripheral. The use of LCD interface limit the bus width to 4 bit
The eMMC and NAND flashes are overlapped, and can be alternatively populated.
=== Memory map ===
For detailed information, please refer to chapter 2 .5 “Memory Maps” organization” of the i.MX Applications Processor STM32MP1 Reference Manual(RM0436).
=== Power supply unit ===