<section begin="History" />
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|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|X.Y.Z{{oldid|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"12862|Month Year2021/02/03}}|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|TBDFirst release
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|-|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|[TBD_link X.Y.Z]|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Month Year|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|TBD|-|! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fbededed; padding:5px; color:#000000"|...2021/12/13|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|...|! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fbededed; padding:5px; color:#000000"|...Add details on BOOT_MODE signals
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<section end="History" /><section begin="Body" />
== System boot ==
* reads the mode pins to determine the primary boot device
* once it is satisfied, it executes the boot code
''TBD: le sezioni di seguito sono valide - come esempio per AXEL Lite - da rivedere per gli altri prodotti ''
== Boot options ==
Two Many options are available related to system for ORCA SOM System boot. They are identified selected by the Boot field of BOOT_MODE[0..2] signals as reported in the ordering code as followsfollowing table:* {| class="wikitable"!BOOT_MODE_2!BOOT_MODE_1!BOOT_MODE_0!BOOT peripheral|-|0|0|0|Boot From Internal Fuses|-|0|0|1|USB Serial Download|-|0: SPI NOR / SD option (SOM code: DXLxxxx0xxR)* |1: NAND / SD option |0|USDHC3 (SOM code: DXLxxxx1xxReMMC boot only, SD3 8-bit)For both options the selection of primary boot device is determined by the BOOT_MODE_SEL signal as described in the following sections. BOOT_MODE_SEL is latched when processor reset is released.|-|0|1|1In any case|USDHC2 (SD boot only, boot process is managed by onSD2)|-chip boot ROM code that is described in detail in processor's Reference Manual.|1|0=== SPI NOR / SD option ===|0Selection of primary boot |NAND 8-bit single device is determined by the BOOT_MODE_SEL signal as follows:256 page|-|1* BOOT_MODE_SEL = |0** primary boot |1|NAND 8-bit single device is SD1512 page|-* boot ROM will try to boot a valid image from the SD card first, and then from the SPI NOR. In case no valid image is found, boot ROM shall enable USB serial download mode automatically|1* BOOT_MODE_SEL = |1 or |0|QSPI 3B Read|}When the signals are left floating** the primary boot device is SPI NOR flash connected set by default to eCSPI1** in case no valid image is found in NOR flash, boot ROM shall enable USB serial download mode automaticallyeMMC on SD3.
=== NAND / SD option ===Selection of primary boot device is determined by the BOOT_MODE_SEL signal as follows:* BOOT_MODE_SEL = The BOOT_MODE[0** primary boot device is SD1** in case no valid image is found in SD card, boot ROM shall enable USB serial download mode automatically * BOOT_MODE_SEL = 1 or floating** primary boot device is NAND flash** in case no valid image ..2] signals are latched when processor reset is found in NAND flash, boot ROM shall enable USB serial download mode automaticallyreleased.
===Important note for DualLite/Solo based products (''manufacture mode'' management)===When Dual Lite or Solo processor are used, GPIO_1 and GPIO_4 signals need to be kept high during bootstrap stage in order The boot process is managed by on-chip boot ROM code: please refer to prevent the intervention of bootromprocessor's ''manufacture mode''. Bootstrap stage has to be intended as the time elapsing between the release of hardware reset (CPU_PORn) and the execution of the first instruction of user code (typically this is the reset vector of U-Boot boot loader). Please note that, in case GPIO_1 signal is used to implement [[Reset_scheme_(AxelLite)#Handling_CPU-initiated_software_reset|software reset circuit]], it is high during bootstrap stage by designReference Manual for more information.
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[[Category:ORCA]]