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__FORCETOC__
<section begin=Body/>
==Peripheral MIPI ==
The MIPI interfaces available on iMX8M SoC are following described:* The ''TBD: sostituire le sezioni con le informazioni sull'uso della perifericaCamera Serial Interface'''(CSI) is a specification of the Mobile Industry Processor Interface (MIPI) Alliance. It defines an interface between a camera and a host processor.* The ''Nell'esempio di seguito cDisplay Serial Interface'è la descrizione dell'interfaccia HDMI''(DSI) is a specification by the Mobile Industry Processor Interface (MIPI) Alliance aimed at reducing the cost of display controllers in a mobile device. It is commonly targeted at LCD and similar display technologies.The two CSI interface on MITO 8M SOM:* CSI1 is avaiable on SODIMM connector pinout* CSI2 is avaiable on ONE PIECE expansion connector J5The DSI interface is internally used on MITO 8M SOM to generate an LVDS output interface. More details on[[MITO 8M SOM/MITO 8M Hardware/Peripherals/LVDS | LVDS section]].
=== Description ===
The MIPI interface available on MITO 8M is based on xxxxx ''TBD:SOC name'' SoC. The MIPI CSI port supports the following standards and features: * High-Definition Multimedia Interface Specification, Version 1.4a * Support for up to 1080p at 60Hz HDTV display resolutions and up to QXGA graphic display resolutions. * Support for 4k x 2k and 3D video formats * Support for up to 16-bit Deep Color modes[[MITO 8M SOM/MITO 8M Hardware/Peripherals/LVDS | LVDS section]]
*Configurable interface logic to support most commonly available CMOS sensors.
*Scalable data lane support, 1 to 4 Data Lanes
*Support for CCIR656 video interface as well as traditional sensor interface.
*8-bit / 16-bit / 24-bit data port for YCbCr, YUV, or RGB data input.
*8-bit / 10-bit / 16-bit data port for Bayer data input.
*Implements all three CSI-2 MIPI layers (Pixel to byte packing, low level protocol, Lane management)
===Pin mapping===