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* MRST* POR* SNVS* SYSRST* ..Hence '''it is recommended that system designer takes into account these factors in order to properly manage these signals at carrier board level'''.

'''TBD: indicare le connessioni del segnale di reset verso altri device interni === EXT_RESET ===EXT_RESET is internally pulled-up with a 90kΩ to NVCC_VSNVS. Connect EXT_RESET signal to GND (come per esempio la NOR SPI'''for example with a button or an open-collector circuit) causes the internal supervisor IC to assert its RESETn output.

=== PMIC_VSNVS ===Some signals that are related to reset circuitry are pulled-up to PMIC_VSNVS. This voltage is generated by Since PMIC_ON serves as the enable signal of PMIC PF0100's VSNVS LDO/Switch and its actual value depends on:other discrete power supply chips, all the power supplies except for the SNVS domain will be OFF.* voltage applied to PMICS's VIN pin** in case of AxelLite this pin The RESETn will keep asserted for 270 ms after EXT_RESET is connected released, thus providing enough time for the power supplies to 3be completely powered down.3VIN power rail* voltage applied to PMICS's LICELL pin** in case of AxelLite During this pin is connected to pin 14 of SODIMM connector time, the POR_B driven by the PMIC will also keep asserted (PMIC_LICELLlow)* PMIC's VSNVSCTL register configuration.Hence '''it is recommended that system designer takes into account these factors in order to properly manage these signals at carrier board level'''.

For more details please refer After RESETn is released, the power supplies will start to section ''VSNVS LDO/Switch'' of ''MMPF0100 Advance Information'' documentramp up in defined sequence. When all the power supplies have reached their operating voltages, POR_B will be de-asserted, and the CPU may begin booting from reset.

The following devices PMIC can assert this active-low signal:. Other internal IC, such as ethernet PHY or boot memory devices, could be connected to this signal. This guarantees it is in a known state when reset signal is released.* PMIC=== CPU_ONOFF ===* multipleCPU_ONOFF is internally pulled-voltage monitor: this device monitors critical up with a 100kΩ to NVCC_VSNVS. This input signal is connected directly to the ONOFF input of the CPU. === BOARD_PGOOD ===BOARD_PGOOD is directly related to the internal NVCC_3V3 rail (I/O pins supply) presence and must be used as power enable for all the electronics on MITO 8M carrier board. When the I/O pins power voltages and triggers a reset pulse rail on MITO 8M is not ready (BOARD_PGOOD low) all the integrated circuits connected to the CPU must be powered off in case any of these exhibits order to avoid back-powering or other issue related to a brownout condition wrong power-up sequence.

Since SPI NOR flash can be used as boot device, CPU_PORn === BOOT_MODE_SEL ===BOOT_MODE_SEL is connected internally pulled-up with a 100kΩ to this device too. This guarantees it is in a known state when reset signal is releasedNVCC_3V3.

'''By default, MX6 MX8 processor does not assert any external signal when it initiates a software reset sequence. Also default software reset implementation does not guarantee that all processor registers are reset properly'''.

For these reasons, it is strongly recommended to use a different approach that, in combination with the use of a processor's watchdog timer (WDT), provides a full hardware reset in case a software reset is issued.

This technique is implemented in [[MITO_8M_SOM/DESK-MX8MX8M-L|DESK-MX8M-L]]. At the software level, U-Boot and Linux kernel software reset routines make use of the processor's WDT #2 to assert the WDOG2_B reset WDOG_B signal. This signal in turn is routed to GPIO_1 the GPIO1_IO02 pad (MUX mode = 1). At the hardware level, this signal is AC-coupled to the master reset pin of the internal supervisor IC. It acts as a 3-state complete hardware reset by the assertion of its RESETn output buffer (please refer to U22 chip on the same way of [[AxelEVB-Lite]] carrier boardEXT_RESET pin), driving PMIC_PWRON.