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MITO 8M SOM/MITO 8M Hardware/Pinout Table

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<section begin="History" />
{| style="border-collapse:collapse; "
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
|-
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0{{oldid| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" 10368|Sep 2020/09/29}}
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |2021/02/02
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |Add pull-up/down information
|-
|}
<section end="History" /><section begin="Body" />==Connectors and Pinout Table=====Introduction=description==
This chapter contains the pinout === Connectors description of ===In the following table are described all available connectors integrated on MITO 8M module, grouped in two tables (odd SOM:{| class="wikitable"|-!Connector name!Connector Type!Notes!Carrier board counterpart|-|J1|SODIMM edge connector 204 pin|partially compatible with [[AXEL Lite SOM]]|TE Connectivity 2-2013289-1|-|J4|ONE PIECE connector single row 25pins||SAMTEC FSI-125-03-G-S-AD-TR|-|J5|ONE PIECE connector single row 25pins||SAMTEC FSI-125-03-G-S-AD-TR|}The dedicated carrier board must mount the mating connector and even pins) that report connect the pin mapping of desired peripheral interfaces according to MITO 8M pinout specifications. See the 204images below for reference: [[File:MITO 8M-pin SOconn-DIMM TOP.png|500px|thumb|MITO 8M connectorTOP view|none]][[File:MITO 8M-conn-BOTTOM.png|500px|thumb|MITO 8M BOTTOM view|none]]
Below a detailed description of the pinout, grouped in the following tables:
* two tables (ODD and EVEN pins) that report the pin mapping of the 204-pin SO-DIMM edge
* a dedicated tables for J4 one-piece connector
* a dedicated tables for J5 one-piece connector
 
=== Pinout Table description ===
Each row in the pinout tables contains the following information:
 {| class="wikitable" style="width:50%;"
|-
|'''Pin'''
|-
|'''Pin Name'''
| Pin (signal) name on the AxelLite MITO 8M connectors
|-
|'''Internal<br>connections'''
| Connections to the Axel Ultra components
* CPU.<x> : pin connected to CPU pad named <x>
* PMIC.<x> : pin connected to the Power Manager IC(NXP PF4210)* LAN.<x> : pin connected to the LAN PHY(MICROCHIP KSZ9031RNX)* BRIDGE.<x> : pin connected to the MIPI-to-LVDS bridge* SV.<x>: pin connected to voltage supervisor(TI SN65DSI84)
|-
|'''Ball/pin #'''
|}
===Pinout Table SODIMM J1 ODD pins declaration ===
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|NVCC_1V8
|I/O
|must Must be level translated if used @ 3V3Internally pulled-up to 1.8V during bootstrap
|
|
|NVCC_1V8
|I/O
|must Must be level translated if used @ 3V3Internally pulled-up to 1.8V during bootstrap
|
|
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for ETH PHY reset, do not connect
|ALT0
|GPIO1_IO01
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |Internally used, do not connect
|ALT0
|GPIO1_IO13
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |Internally used for MIPI-to-LVDS interrupt, do not connectPulled-up to NVCC_3V3
|ALT0
|GPIO1_IO05
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for MIPI-to-LVDS enable, do not connect
|ALT0
|GPIO1_IO06
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|SDMA1_EXT_EVENT0
|-
| rowspan="3" |J1.187|UART1_TXDrowspan="3" |UART2_TXD|???rowspan="3" |CPU.UART2_TXD|rowspan="3" |D6| rowspan="3" |NVCC_3V3| rowspan="3" |I/O|rowspan="3" |used as default Linux console|ALT0|UART2_TX
|-
|J1.189|UART1_RXD|???||NVCC_3V3|I/O||ALT1|ECSPI3_SS0
|-
|J1.191|UART2_TXD|???||NVCC_3V3|I/O||ALT5|GPIO5_IO25
|-
|J1.193|UART2_RXD|???||NVCC_3V3|I/O||||-| rowspan="3" |J1.195189| rowspan="3" |ECSPI1_MOSIUART2_RXD| rowspan="3" |CPU.ECSPI1_MOSIUART2_RXD| rowspan="3" |A4B6
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |used as default Linux console|ALT0|UART2_RXD|-|ALT1|ECSPI3_MISO|-|ALT5|GPIO5_IO24|-| rowspan="3" |J1.191| rowspan="3" |UART1_TXD| rowspan="3" |CPU.UART1_TXD| rowspan="3" |A7| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|UART1_TX|-|ALT1|ECSPI3_MOSI|-|ALT5|GPIO5_IO23|-| rowspan="3" |J1.193| rowspan="3" |UART1_RXD| rowspan="3" |CPU.UART1_RXD| rowspan="3" |C7| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|UART1_RXD|-|ALT1|ECSPI3_SCLK|-|ALT5|GPIO5_IO22|-| rowspan="3" |J1.195| rowspan="3" |ECSPI1_MOSI| rowspan="3" |CPU.ECSPI1_MOSI| rowspan="3" |A4| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" |
|ALT0
|ECSPI1_MOSI
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|}
===Pinout Table SODIMM J1 EVEN pins declaration ===
{| class="wikitable"
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
! colspan="2" latexfontsize="scriptsize" | Alternative Functions
|-
|J1.2
|<nowiki>-</nowiki>
|G
|
|
|
|3.3VIN
|S
|
|
|
|3.3VIN
|S
|
|
|
|3.3VIN
|S
|
|
|
|3.3VIN
|S
|
|
|
|<nowiki>-</nowiki>
|G
|
|
|
| -
|S
|
|
|
|I
|internal pull-up 100k to NVCC_SNVS
|
|
|-
|NVCC_3V3
|O
|
|
|
|I
|internal pull-up to NVCC_3V3
|
|
|-
|I/O
|internal pull-up 100k to NVCC_SNVS
|
|
|-
|I
|internal pull-up to NVCC_SNVS
|
|
|-
| rowspan="4" |J1.26| rowspan="4" |SAI3_RXC| rowspan="4" |CPU.SAI3_RXC| rowspan="4" |F4| rowspan="4" |NVCC_3V3| rowspan="4" |I/O|rowspan="4" ||ALT0|SAI3_RX_BCLK|-|ALT1|GPT1_CAPTURE2|-|ALT2|SAI5_RX_BCLK|-|ALT5|GPIO4_IO29
|-
| rowspan="4" |J1.28| rowspan="4" |GPIO1_IO02| rowspan="4" |CPU.GPIO1_IO02| rowspan="4" |R4| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" |Internally used for SW reset, do not connect|ALT0
|GPIO1_IO02
|CPU.GPIO1_IO02
|R4
|NVCC_3V3
|I/O
|
|
|-
|ALT1|WDOG1_WDOG_B|-|ALT5|WDOG1_WDOG_ANY|-|ALT7|SJC_DE_B|-|J1.30
|DGND
|DGND
|<nowiki>-</nowiki>
|G
|
|
|
|-
| rowspan="4" |J1.32| rowspan="4" |SAI3_RXD| rowspan="4" |CPU.SAI3_RXD| rowspan="4" |F3| rowspan="4" |NVCC_3V3| rowspan="4" |I/O|rowspan="4" ||ALT0|SAI3_RX_DATA0
|-
|J1.34|SAI2_MCLK|CPU.SAI2_MCLK|H5|NVCC_3V3|I/O|ALT1|GPT1_COMPARE1
|-
|J1.36|SAI3_RXFS|CPU.SAI3_RXFS|G4|NVCC_3V3|I/O|ALT2|SAI5_RX_DATA0
|-
|J1.38|I2C3_SCL|CPU.I2C3_SCL|G8|NVCC_3V3|I/O|ALT5|GPIO4_IO30
|-
| rowspan="3" |J1.4034|SAI3_TXFSrowspan="3" |SAI2_MCLK| rowspan="3" |CPU.SAI3_TXFSSAI2_MCLK|G3rowspan="3" |H5| rowspan="3" |NVCC_3V3| rowspan="3" |I/O|rowspan="3" ||ALT0|SAI2_MCLK
|-
|J1.42|SPDIF_RX|CPU.SPDIF_RX|G6|NVCC_3V3|I/O|ALT1|SAI5_MCLK
|-
|J1.44|SPDIF_TX|CPU.SPDIF_TX|F6|NVCC_3V3|I/O|ALT5|GPIO4_IO27
|-
| rowspan="4" |J1.4636|SAI3_MCLKrowspan="4" |SAI3_RXFS| rowspan="4" |CPU.SAI3_MCLKSAI3_RXFS|D3rowspan="4" |G4| rowspan="4" |NVCC_3V3| rowspan="4" |I/O|rowspan="4" ||ALT0|SAI3_RX_SYNC
|-
|J1.48|I2C3_SDA|CPU.I2C3_SDA|E9|NVCC_3V3|I/O|ALT1|GPT1_CAPTURE1
|-
|J1.50ALT2|SAI3_TXCSAI5_RX_SYNC|CPU.SAI3_TXC|C4|NVCC_3V3|I/O-|ALT5|GPIO4_IO28
|-
| rowspan="4" |J1.5238|SAI3_TXDrowspan="4" |I2C3_SCL| rowspan="4" |CPU.SAI3_TXDI2C3_SCL|C3rowspan="4" |G8| rowspan="4" |NVCC_3V3| rowspan="4" |I/O|rowspan="4" ||ALT0|I2C3_SCL
|-
|J1.54|SD1_STROBE|CPU.SD1_STROBE|T24|NVCC_1V8 // NVCC_3V3 ???|I/O|internally used for eMMCALT1|PWM4_OUT
|-
|J1.56|DGND|DGND| -|<nowiki>-</nowiki>|G|ALT2|GPT2_CLK
|-
|J1.58|SAI5_MCLK|CPU.SAI5_MCLK|K4|NVCC_3V3|I/O|ALT5|GPIO5_IO18
|-
| rowspan="4" |J1.6040|GPIO1_IO15rowspan="4" |SAI3_TXFS| rowspan="4" |CPU.GPIO1_IO15SAI3_TXFS|J6rowspan="4" |G3| rowspan="4" |NVCC_3V3| rowspan="4" |I/O|rowspan="4" ||ALT0|SAI3_TX_SYNC
|-
|J1.62|SAI5_RXFS|CPU.SAI5_RXFS|N4|NVCC_3V3|I/O|ALT1|GPT1_CLK
|-
|J1.64|SAI5_RXC|CPU.SAI5_RXC|L5|NVCC_3V3|I/O|ALT2|SAI5_RX_DATA1
|-
|J1.66|SAI2_TXC|CPU.SAI2_TXC|J5|NVCC_3V3|I/O|ALT5|GPIO4_IO31
|-
| rowspan="3" |J1.6842|SAI2_TXD0rowspan="3" |SPDIF_RX| rowspan="3" |CPU.SAI2_TXD0SPDIF_RX|G5rowspan="3" |G6| rowspan="3" |NVCC_3V3| rowspan="3" |I/O|rowspan="3" ||ALT0|SPDIF1_IN
|-
|J1.70|SAI2_TXFS|CPU.SAI2_TXFS|H4|NVCC_3V3|I/O|ALT1|PWM2_OUT
|-
|J1.72|SAI2_RXD0|CPU.SAI2_RXD0|H6|NVCC_3V3|I/O|ALT5|GPIO5_IO04
|-
| rowspan="3" |J1.7444|SAI5_RXD0rowspan="3" |SPDIF_TX| rowspan="3" |CPU.SAI5_RXD0SPDIF_TX|M5rowspan="3" |F6| rowspan="3" |NVCC_3V3| rowspan="3" |I/O|rowspan="3" ||ALT0|SPDIF1_OUT
|-
|J1.76|SAI5_RXD1|CPU.SAI5_RXD1|L4|NVCC_3V3|I/O|ALT1|PWM3_OUT
|-
|J1.78|SAI5_RXD2|CPU.SAI5_RXD2|M4|NVCC_3V3|I/O|ALT5|GPIO5_IO03
|-
| rowspan="4" |J1.8046|SAI5_RXD3rowspan="4" |SAI3_MCLK| rowspan="4" |CPU.SAI5_RXD3SAI3_MCLK|K5rowspan="4" |D3| rowspan="4" |NVCC_3V3| rowspan="4" |I/O|rowspan="4" ||ALT0|SAI3_MCLK
|-
|J1.82|DGND|DGND| -|<nowiki>-</nowiki>|G|ALT1|PWM4_OUT
|-
|J1.84|CLK2_N|CPU.CLK2_N|T22|VDDA_1V8|D|ALT2|SAI5_MCLK
|-
|J1.86|CLK2_P|CPU.CLK2_P|U22|VDDA_1V8|D|ALT5|GPIO5_IO02
|-
| rowspan="4" |J1.8848|PCIE1_REF_CLKNrowspan="4" |I2C3_SDA| rowspan="4" |CPU.PCIE1_REF_PAD_CLK_NI2C3_SDA|K24rowspan="4" |E9|VDD_PHY_3V3rowspan="4" |NVCC_3V3|Drowspan="4" |I/O| rowspan="4" ||ALT0|I2C3_SDA
|-
|J1.90|PCIE1_REF_CLKP|CPU.PCIE1_REF_PAD_CLK_P|K25|VDD_PHY_3V3|D|ALT1|PWM3_OUT
|-
|J1.92|PCIE1_RXN|CPU.PCIE1_RXN_N|H24|VDD_PHY_3V3|D|ALT2|GPT3_CLK
|-
|J1.94|PCIE1_RXP|CPU.PCIE1_RXN_P|H25|VDD_PHY_3V3|D|ALT5|GPIO5_IO19
|-
| rowspan="4" |J1.9650|PCIE1_TXNrowspan="4" |SAI3_TXC| rowspan="4" |CPU.PCIE1_TXN_NSAI3_TXC| rowspan="4" |C4| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||J24ALT0|VDD_PHY_3V3SAI3_TX_BCLK|D-|ALT1|GPT1_COMPARE2
|-
|J1.98|PCIE1_TXP|CPU.PCIE1_TXN_P|J25|VDD_PHY_3V3|D|ALT2|SAI5_RX_DATA2
|-
|J1.100|DGND|DGND| -|<nowiki>-</nowiki>|G|ALT5|GPIO5_IO00
|-
| rowspan="4" |J1.52| rowspan="4" |SAI3_TXD| rowspan="4" |CPU.SAI3_TXD| rowspan="4" |C3| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI3_TX_DATA0|-|ALT1|GPT1_COMPARE3|-|ALT2|SAI5_RX_DATA3|-|ALT5|GPIO5_IO01|-| rowspan="2" |J1.10254|CSI1_CLK_Nrowspan="2" |GPIO1_IO10| rowspan="2" |CPU.MIPI_CSI1_CLK_NGPIO1_IO10| rowspan="2" |M7| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" |Internally used for ETH PHY interrupt, do not connect|ALT0|GPIO1_IO10|-|ALT1|USB1_OTG_ID|-|J1.56|DGND|A22DGND
| -
|D<nowiki>-</nowiki>|G
|
|
|-
|J1.104
|CSI1_CLK_P
|CPU.MIPI_CSI1_CLK_P
|B22
| -
|D
|
|
|-
| rowspan="4" |J1.10658|CSI1_D0_Nrowspan="4" |SAI5_MCLK| rowspan="4" |CPU.MIPI_CSI1_D0_NSAI5_MCLK|A23rowspan="4" |K4| -rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI5_MCLK|D-|ALT1|SAI1_TX_BCLK
|-
|J1.108|CSI1_D0_P|CPU.MIPI_CSI1_D0_P|B23| -|D|ALT2|SAI4_MCLK
|-
|J1.110|CSI1_D1_N|CPU.MIPI_CSI1_D1_N|C22| -|D|ALT5|GPIO3_IO25
|-
| rowspan="4" |J1.11260|CSI1_D1_Prowspan="4" |GPIO1_IO15| rowspan="4" |CPU.MIPI_CSI1_D1_PGPIO1_IO15|D22rowspan="4" |J6| -rowspan="4" |NVCC_3V3|Drowspan="4" |I/O| rowspan="4" ||ALT0|GPIO1_IO15
|-
|J1.114|CSI1_D2_N|CPU.MIPI_CSI1_D2_N|B24| -|D|ALT1|USB2_OTG_OC
|-
|J1.116|CSI1_D2_P|CPU.MIPI_CSI1_D2_P|C23| -|D|ALT5|PWM4_OUT
|-
|J1.118|CSI1_D3_N|CPU.MIPI_CSI1_D3_N|C21| -|D|ALT6|CCM_CLKO2
|-
| rowspan="3" |J1.12062|CSI1_D3_Prowspan="3" |SAI5_RXFS| rowspan="3" |CPU.MIPI_CSI1_D3_PSAI5_RXFS|D21rowspan="3" |N4| -rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| rowspan="3" ||ALT0|SAI5_RX_SYNC
|-
|J1.122|DGND|DGND| -|<nowiki>-</nowiki>|G|ALT1|SAI1_TX_DATA0
|-
|J1.124|NAND_DQS|CPU.NAND_DQS|M20|NVCC_3V3|I/O|internally used for NANDALT5|GPIO3_IO19
|-
| rowspan="3" |J1.12664|NAND_ALErowspan="3" |SAI5_RXC| rowspan="3" |CPU.NAND_ALESAI5_RXC|G19rowspan="3" |L5| rowspan="3" |NVCC_3V3| rowspan="3" |I/O|internally used for NANDrowspan="3" ||ALT0|SAI5_RX_BCLK
|-
|J1.128|NAND_CE0_B // SD1_CLK|CPU.NAND_CE0_B // CPU.SD1_CLK|H19 // L25|NVCC_1V8 // NVCC_3V3 ???|I/O|???ALT1|SAI1_TX_DATA1
|-
|J1.130|NAND_CE1_B // SD1_CMD|CPU.NAND_CE1_B // CPU.SD1_CMD|G21 // L24|NVCC_1V8 // NVCC_3V3 ???|I/O|???ALT5|GPIO3_IO20
|-
| rowspan="3" |J1.13266|NAND_CE2_B // SD1_RST_Browspan="3" |SAI2_TXC| rowspan="3" |CPU.NAND_CE2_B // CPU.SD1_RST_BSAI2_TXC|F21 // R24rowspan="3" |J5|NVCC_1V8 // rowspan="3" |NVCC_3V3 ???| rowspan="3" |I/O|???rowspan="3" ||ALT0|SAI2_TX_BCLK
|-
|J1.134|NAND_CE3_B // SD1_STROBE|CPU.NAND_CE3_B // CPU.SD1_STROBE|H20 // T24|NVCC_1V8 // NVCC_3V3 ???|I/O|???ALT1|SAI5_TX_DATA2
|-
|J1.136|NAND_CLE|DGND|H21|NVCC_3V3|I/O|ALT5|GPIO4_IO25
|-
| rowspan="3" |J1.13868|NAND_DATA00 // SD1_DATA0rowspan="3" |SAI2_TXD0| rowspan="3" |CPU.NAND_DATA00 // CPU.SD1_DATA0SAI2_TXD0|G20 // M25rowspan="3" |G5|NVCC_1V8 // rowspan="3" |NVCC_3V3 ???| rowspan="3" |I/O|???rowspan="3" ||ALT0|SAI2_TX_DATA0
|-
|J1.140|NAND_DATA01 // SD1_DATA1|CPU.NAND_DATA01 // CPU.SD1_DATA1|J20 // M24|NVCC_1V8 // NVCC_3V3 ???|I/O|???ALT1|SAI5_TX_DATA3
|-
|J1.142|NAND_DATA02 // SD1_DATA2|CPU.NAND_DATA02 // CPU.SD1_DATA2|H22 // N25|NVCC_1V8 // NVCC_3V3 ???|I/O|???ALT5|GPIO4_IO26
|-
| rowspan="3" |J1.14470|NAND_DATA03 // SD1_DATA3rowspan="3" |SAI2_TXFS| rowspan="3" |CPU.NAND_DATA03 // CPU.SD1_DATA3SAI2_TXFS|J21 // P25rowspan="3" |H4|NVCC_1V8 // rowspan="3" |NVCC_3V3 ???| rowspan="3" |I/O|???rowspan="3" ||ALT0|SAI2_TX_SYNC
|-
|J1.146|DGND|DGND| -|<nowiki>-</nowiki>|G|ALT1|SAI5_TX_DATA1
|-
|J1.148|NAND_DATA04 // SD1_DATA4|CPU.NAND_DATA04 // CPU.SD1_DATA4|L20 // N24|NVCC_1V8 // NVCC_3V3 ???|I/O|???ALT5|GPIO4_IO24
|-
| rowspan="3" |J1.15072|NAND_DATA05 // SD1_DATA5rowspan="3" |SAI2_RXD0| rowspan="3" |CPU.NAND_DATA05 // CPU.SD1_DATA5SAI2_RXD0|J22 // P24rowspan="3" |H6|NVCC_1V8 // rowspan="3" |NVCC_3V3 ???| rowspan="3" |I/O|???rowspan="3" ||ALT0|SAI2_RX_DATA0
|-
|J1.152|NAND_DATA06 // SD1_DATA6|CPU.NAND_DATA06 // CPU.SD1_DATA6|L19 // R25|NVCC_1V8 // NVCC_3V3 ???|I/O|???ALT1|SAI5_TX_DATA0
|-
|J1.154|NAND_DATA07 // SD1_DATA7|CPU.NAND_DATA07 // CPU.SD1_DATA7|M19 // T25|NVCC_1V8 // NVCC_3V3 ???|I/O|???ALT5|GPIO4_IO23
|-
| rowspan="3" |J1.15674|NAND_RE_Browspan="3" |SAI5_RXD0| rowspan="3" |CPU.NAND_RE_BSAI5_RXD0|K19rowspan="3" |M5| rowspan="3" |NVCC_3V3| rowspan="3" |I/O|rowspan="3" ||ALT0|SAI5_RX_DATA0 |-|ALT1|SAI1_TX_DATA2
|-
|J1.158|NAND_READY_B|CPU.NAND_READY_B|K20|NVCC_3V3|I/O|ALT5|GPIO3_IO21
|-
| rowspan="5" |J1.16076|NAND_WE_Browspan="5" |SAI5_RXD1| rowspan="5" |CPU.NAND_WE_BSAI5_RXD1|K22rowspan="5" |L4| rowspan="5" |NVCC_3V3| rowspan="5" |I/O|rowspan="5" ||ALT0|SAI5_RX_DATA1
|-
|ALT1|SAI1_TX_DATA3|-|ALT2|SAI1_TX_SYNC|-|ALT3|SAI5_TX_SYNC|-|ALT5|GPIO3_IO212|-| rowspan="5" |J1.78| rowspan="5" |SAI5_RXD2| rowspan="5" |CPU.SAI5_RXD2| rowspan="5" |M4| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" ||ALT0|SAI5_RX_DATA2|-|ALT1|SAI1_TX_DATA4|-|ALT2|SAI1_TX_SYNC|-|ALT3|SAI5_TX_BCLK|-|ALT5|GPIO3_IO23|-| rowspan="5" |J1.16280|NAND_WP_Browspan="5" |SAI5_RXD3| rowspan="5" |CPU.NAND_WP_BSAI5_RXD3|K21rowspan="5" |K5| rowspan="5" |NVCC_3V3| rowspan="5" |I/O|rowspan="5" ||ALT0|SAI5_RX_DATA3|-|ALT1|SAI1_TX_DATA5|-|ALT2|SAI1_TX_SYNC|-|ALT3|SAI5_TX_DATA0|-|ALT5|GPIO3_IO24
|-
|J1.16482
|DGND
|DGND
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J1.16684|CLK1_NCLK2_N|CPU.CLK1_NCLK2_N|T23T22|VDDA_1V8
|D
|Internally used for PCIe CLK, do not connect
|
|
|-
|J1.16886|CLK1_PCLK2_P|CPU.CLK1_PCLK2_P|R23U22|VDDA_1V8
|D
|Internally used for PCIe CLK, do not connect
|
|
|-
|J1.17088|USB2_RXNPCIE1_REF_CLKN|CPU.USB2_RX_NPCIE1_REF_PAD_CLK_N|B8K24|VDD_PHY_3V3|D
|
|D
|
|
|-
|J1.17290|USB2_RXPPCIE1_REF_CLKP|CPU.USB2_RX_PPCIE1_REF_PAD_CLK_P|A8K25|VDD_PHY_3V3|D
|
|D
|
|
|-
|J1.17492|USB2_TXNPCIE1_RXN|CPU.USB2_TX_NPCIE1_RXN_N|B9H24|VDD_PHY_3V3|D
|
|D
|
|
|-
|J1.17694|USB2_TXPPCIE1_RXP|CPU.USB2_TX_PPCIE1_RXN_P|A9H25|VDD_PHY_3V3
|D
|
|
|-
|J1.178
|USB1_RXN
|CPU.USB1_RX_N
|B12
|
|D
|
|
|-
|J1.18096|USB1_RXPPCIE1_TXN|CPU.USB1_RX_PPCIE1_TXN_N|A12J24|VDD_PHY_3V3|D
|
|D
|
|
|-
|J1.18298|USB1_TXNPCIE1_TXP|CPU.USB1_TX_NPCIE1_TXN_P|B13J25|VDD_PHY_3V3|D
|
|D
|
|
|-
|J1.184100|USB1_TXPDGND|CPU.USB1_TX_PDGND|A13-|<nowiki>-</nowiki>|G
|
|D
|
|
|-
|J1.186102|USB1_VBUSCSI1_CLK_N|CPU.USB1_VBUSMIPI_CSI1_CLK_N|D14A22
| -
|SD|
|
|
|-
|J1.188104|USB2_VBUSCSI1_CLK_P|CPU.USB2_VBUSMIPI_CSI1_CLK_P|D9B22
| -
|SD|
|
|
|-
|J1.190106|DGNDCSI1_D0_N|DGNDCPU.MIPI_CSI1_D0_N|A23
| -
|<nowiki>-</nowiki>D|G
|
|
|-
|J1.192108|USB1_IDCSI1_D0_P|CPU.USB1_IDMIPI_CSI1_D0_P|C14B23|VDD_PHY_3V3|I-|D
|
|-
|J1.194
|USB2_ID
|CPU.USB2_ID
|C9
|VDD_PHY_3V3
|I
|
|
|-
|J1.196110|USB1_DNCSI1_D1_N|CPU.USB1_DNMIPI_CSI1_D1_N|B14C22
| -
|D
|
|
|
|-
|J1.198112|USB1_DPCSI1_D1_P|CPU.USB1_DPMIPI_CSI1_D1_P|A14D22
| -
|D
|
|
|
|-
|J1.200114|USB2_DPCSI1_D2_N|CPU.USB2_DPMIPI_CSI1_D2_N|A10B24
| -
|D
|
|
|
|-
|J1.202116|USB2_DNCSI1_D2_P|CPU.USB2_DNMIPI_CSI1_D2_P|B10C23
| -
|D
|
|
|
|-
|J1.204118|DGNDCSI1_D3_N|DGNDCPU.MIPI_CSI1_D3_N|C21
| -
|<nowiki>-</nowiki>D|G
|
|
|-
|}J1.120 ===Pinout Table J4 pins declaration ==={| class="wikitable" CSI1_D3_P! latexfontsize="scriptsize" | Pin CPU.MIPI_CSI1_D3_P! latexfontsize="scriptsize" | Pin NameD21! latexfontsize="scriptsize" | Internal Connections -! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>D! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! latexfontsize="scriptsize" | Alternative Functions
|-
|J4J1.1122
|DGND
|DGND
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J4J1.2124(NAND on board)|SAI1_RXD7NAND_DQS|CPU.SAI1_RXD7NAND_DQS|G1M20
|NVCC_3V3
|I/O
|internally Internally used for BOOT configNAND, do not connect|
|
|-
|J4rowspan="3" |J1.124(eMMC on board)| rowspan="3" |NAND_DQS| rowspan="3" |CPU.NAND_DQS| rowspan="3" |M20| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DQS|-|ALT1|QSPI_A_DQS|-|ALT5|GPIO3_IO14|-|J1.126(NAND on board)|SAI1_RXD6NAND_ALE|CPU.SAI1_RXD6NAND_ALE|G2G19
|NVCC_3V3
|I/O
|internally Internally used for BOOT configNAND, do not connect
|
|-
|J4.4
|SAI1_RXD5
|CPU.SAI1_RXD5
|F1
|NVCC_3V3
|I/O
|internally used for BOOT config
|
|-
|J4rowspan="3" |J1.5126(eMMC on board)|SAI1_RXD4rowspan="3" |NAND_ALE| rowspan="3" |CPU.SAI1_RXD4NAND_ALE|J1rowspan="3" |G19| rowspan="3" |NVCC_3V3| rowspan="3" |I/O|internally used for BOOT configrowspan="3" ||ALT0|RAWNAND_ALE
|-
|J4.6|SAI1_RXD3|CPU.SAI1_RXD3|J2|NVCC_3V3|I/O|internally used for BOOT configALT1|QSPI_A_SCLK
|-
|J4.7|SAI1_RXD2|CPU.SAI1_RXD2|H2|NVCC_3V3|I/O|internally used for BOOT configALT5|GPIO3_IO00
|-
|J4rowspan="2" |J1.8128(NAND on board)| rowspan="2" |SAI1_RXD1SD1_CLK| rowspan="2" |CPU.SAI1_RXD1SD1_CLK|L2rowspan="2" |L25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O|internally used for BOOT configrowspan="2" ||ALT0|USDHC1_CLK
|-
|J4.9|SAI1_RXD0|CPU.SAI1_RXD0|K2|NVCC_3V3|I/O|internally used for BOOT configALT5|GPIO2_IO00
|-
|J4rowspan="3" |J1.10128(eMMC on board)|SAI1_RXCrowspan="3" |NAND_CE0_B| rowspan="3" |CPU.SAI1_RXCNAND_CE0_B|K1rowspan="3" |H19| rowspan="3" |NVCC_3V3| rowspan="3" |I/O|rowspan="3" ||ALT0|RAWNAND_CE0_B
|-
|J4.11|SAI1_RXFS|CPU.SAI1_RXFS|L1|NVCC_3V3|I/O|ALT1|QSPI_A_SS0_B
|-
|J4.12|DGND|DGND| -|<nowiki>-</nowiki>|G|ALT5|GPIO3_IO01
|-
|J4rowspan="2" |J1.13130(NAND on board)| rowspan="2" |SAI1_MCLKSD1_CMD| rowspan="2" |CPU.SAI1_MCLKSD1_CMD|rowspan="2" |L24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O|rowspan="2" ||ALT0|USDHC1_CMD
|-
|J4.14|DGND|DGND| -|<nowiki>-</nowiki>|G|ALT5|GPIO2_IO01
|-
|J4rowspan="3" |J1.15130(eMMC on board)|SAI1_TXFSrowspan="3" |NAND_CE1_B| rowspan="3" |CPU.SAI1_TXFSNAND_CE1_B|H4rowspan="3" |G21| rowspan="3" |NVCC_3V3| rowspan="3" |I/O|rowspan="3" ||ALT0|RAWNAND_CE1_B
|-
|J4.16|SAI1_TXC|CPU.SAI1_TXC|J5|NVCC_3V3|I/O|ALT1|QSPI_A_SS1_B
|-
|J4.17|SAI1_TXD0|CPU.SAI1_TXD0|F2|NVCC_3V3|I/O|internally used for BOOT configALT5|GPIO3_IO02
|-
|J4rowspan="2" |J1.18132(NAND on board)| rowspan="2" |SAI1_TXD1SD1_RST_B| rowspan="2" |CPU.SAI1_TXD1SD1_RST_B|E2rowspan="2" |R24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O|internally used for BOOT configrowspan="2" ||ALT0|USDHC1_RESET_B
|-
|J4.19|SAI1_TXD2|CPU.SAI1_TXD2|B2|NVCC_3V3|I/O|internally used for BOOT configALT5|GPIO2_IO10
|-
|J4rowspan="3" |J1.20132(eMMC on board)|SAI1_TXD3rowspan="3" |NAND_CE2_B| rowspan="3" |CPU.SAI1_TXD3NAND_CE2_B|D1rowspan="3" |F21| rowspan="3" |NVCC_3V3| rowspan="3" |I/O|internally used for BOOT configrowspan="3" ||ALT0|RAWNAND_CE2_B
|-
|J4ALT1|QSPI_B_SS0_B|-|ALT5|GPIO3_IO03|-| rowspan="2" |J1.134(NAND on board)| rowspan="2" |SD1_STROBE| rowspan="2" |CPU.SD1_STROBE| rowspan="2" |T24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_STROBE|-|ALT5|GPIO2_IO11|-| rowspan="3" |J1.21134(eMMC on board)|SAI1_TXD4rowspan="3" |NAND_CE3_B| rowspan="3" |CPU.SAI1_TXD4NAND_CE3_B|D2rowspan="3" |H20| rowspan="3" |NVCC_3V3| rowspan="3" |I/O|internally used for BOOT configrowspan="3" ||ALT0|RAWNAND_CE3_B|-|ALT1|QSPI_B_SS1_B
|-
|J4.22|SAI1_TXD5|CPU.SAI1_TXD5|C2|NVCC_3V3|I/O|internally used for BOOT configALT5|GPIO3_IO034
|-
|J4J1.23136(NAND on board)|SAI1_TXD6NAND_CLE|CPU.SAI1_TXD6NAND_CLE|B3H21
|NVCC_3V3
|I/O
|internally Internally used for BOOT configNAND, do not connect
|
|-
|J4.24
|SAI1_TXD7
|CPU.SAI1_TXD7
|C1
|NVCC_3V3
|I/O
|internally used for BOOT config
|
|-
|J4rowspan="3" |J1.25|DGND|DGND| -136|<nowiki>-</nowiki>(eMMC on board)|G|||}===Pinout Table J5 pins declaration ==={| classrowspan="wikitable3" |NAND_CLE! latexfontsize| rowspan="scriptsize3" | Pin CPU.NAND_CLE! latexfontsize| rowspan="scriptsize3" | Pin NameH21! latexfontsize| rowspan="scriptsize3" | Internal Connections NVCC_3V3! latexfontsize| rowspan="scriptsize3" | BallI/pin # O! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>! latexfontsizerowspan="scriptsize3" | Type ! latexfontsize="scriptsize" | NotesALT0! latexfontsize="scriptsize" | Alternative FunctionsRAWNAND_CLE
|-
|J5.1|DGND|DGND| -|<nowiki>-</nowiki>|G|ALT1|QSPI_B_SCLK
|-
|J5.2|PCIE2_RXN|CPU.PCIE2_RXN_N|D24| -|D|ALT5|GPIO3_IO05
|-
|J5rowspan="2" |J1.3138(NAND on board)|PCIE2_RXProwspan="2" |SD1_DATA0| rowspan="2" |CPU.PCIE2_RXN_PSD1_DATA0| rowspan="2" |M25|D25rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| -rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA0|D-|ALT5|GPIO2_IO02
|-
|J5rowspan="3" |J1.4138(eMMC on board)| rowspan="3" |DGNDNAND_DATA00|DGNDrowspan="3" |CPU.NAND_DATA00| -rowspan="3" |G20|<nowiki>-<rowspan="3" |NVCC_3V3| rowspan="3" |I/nowiki>O|Growspan="3" ||ALT0|RAWNAND_DATA00
|-
|J5.5|PCIE2_TXN|CPU.PCIE2_TXN_N|E24| -|D|ALT1|QSPI_A_DATA0
|-
|J5.6|PCIE2_TXP|CPU.PCIE2_TXN_P|E25| -|D|ALT5|GPIO3_IO06
|-
|J5rowspan="2" |J1.7140(NAND on board)| rowspan="2" |SD1_DATA1|DGNDrowspan="2" |CPU.SD1_DATA1|DGNDrowspan="2" |M24| -rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|<nowiki>-<rowspan="2" |I/nowiki>O|Growspan="2" ||ALT0|USDHC1_DATA1
|-
|J5.8|PCIE2_REF_CLKN|CPU.PCIE2_REF_PAD_CLK_N|F24| -|D|ALT5|GPIO2_IO0
|-
|J5rowspan="3" |J1.9140(eMMC on board)|PCIE2_REF_CLKProwspan="3" |NAND_DATA01| rowspan="3" |CPU.PCIE2_REF_PAD_CLK_PNAND_DATA01| rowspan="3" |J20|F25rowspan="3" |NVCC_3V3| -rowspan="3" |I/O|Drowspan="3" ||ALT0|RAWNAND_DATA01
|-
|J5.10|DGND|DGND| -|<nowiki>-</nowiki>|G|ALT1|QSPI_A_DATA1
|-
|J5.11|CSI_P2_CKN|CPU.MIPI_CSI2_CLK_N|A19| -|D|ALT5|GPIO3_IO07
|-
|J5rowspan="2" |J1.12142(NAND on board)| rowspan="2" |CSI_P2_CKPSD1_DATA2| rowspan="2" |CPU.MIPI_CSI2_CLK_PSD1_DATA2|B19rowspan="2" |N25| -rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" |D|ALT0|USDHC1_DATA2
|-
|J5ALT5|GPIO2_IO04|-| rowspan="3" |J1.13142(eMMC on board)| rowspan="3" |NAND_DATA02| rowspan="3" |CPU.NAND_DATA02| rowspan="3" |H22| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA02|-|ALT1|QSPI_A_DATA2|-|ALT5|GPIO3_IO08|-| rowspan="2" |J1.144(NAND on board)| rowspan="2" |SD1_DATA3| rowspan="2" |CPU.SD1_DATA3| rowspan="2" |P25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA3|-|ALT5|GPIO2_IO05|-| rowspan="3" |J1.144(eMMC on board)| rowspan="3" |NAND_DATA03| rowspan="3" |CPU.NAND_DATA03| rowspan="3" |J21| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA03|-|ALT1|QSPI_A_DATA3|-|ALT5|GPIO3_IO09|-|J1.146
|DGND
|DGND
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5rowspan="2" |J1.14148(NAND on board)|CSI_P2_DN0rowspan="2" |SD1_DATA4| rowspan="2" |CPU.MIPI_CSI2_D0_NSD1_DATA4|C20rowspan="2" |N24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA4| -|DALT5|GPIO2_IO06|-| rowspan="3" |J1.148(eMMC on board)| rowspan="3" |NAND_DATA04| rowspan="3" |CPU.NAND_DATA04| rowspan="3" |L20| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA04
|-
|J5.15|CSI_P2_DP0|CPU.MIPI_CSI2_D0_P|D10| -|D|ALT1|QSPI_B_DATA0
|-
|J5.16|CSI_P2_DN1|CPU.MIPI_CSI2_D1_N|A20| -|D|ALT5|GPIO3_IO10
|-
|J5rowspan="2" |J1.17150(NAND on board)|CSI_P2_DP1rowspan="2" |SD1_DATA5| rowspan="2" |CPU.MIPI_CSI2_D1_PSD1_DATA5| rowspan="2" |P24|B20rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| -rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA5|D-|ALT5|GPIO2_IO07
|-
|J5rowspan="3" |J1.18150(eMMC on board)| rowspan="3" |DGNDNAND_DATA05|DGNDrowspan="3" |CPU.NAND_DATA05| -rowspan="3" |J22|<nowiki>-<rowspan="3" |NVCC_3V3| rowspan="3" |I/nowiki>O|Growspan="3" ||ALT0|RAWNAND_DATA05
|-
|J5.19|CSI_P2_DN2|CPU.MIPI_CSI2_D2_N|A21| -|D|ALT1|QSPI_B_DATA1
|-
|J5.20|CSI_P2_DP2|CPU.MIPI_CSI2_D2_P|B21| -|D|ALT5|GPIO3_IO11
|-
|J5rowspan="2" |J1.21152(NAND on board)| rowspan="2" |CSI_P2_DN3SD1_DATA6| rowspan="2" |CPU.MIPI_CSI2_D3_NSD1_DATA6|C19rowspan="2" |R25| -rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" |D|ALT0|USDHC1_DATA6
|-
|J5.22|CSI_P2_DP3|CPU.MIPI_CSI2_D3_P|D19| -|D|ALT5|GPIO2_IO08
|-
|J5rowspan="3" |J1.152(eMMC on board)| rowspan="3" |NAND_DATA06| rowspan="3" |CPU.23NAND_DATA06| rowspan="3" |L19| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||DGNDALT0|DGNDRAWNAND_DATA06| -|<nowiki>ALT1|QSPI_B_DATA2|-<|ALT5|GPIO3_IO12|-| rowspan="2" |J1.154(NAND on board)| rowspan="2" |SD1_DATA7| rowspan="2" |CPU.SD1_DATA7| rowspan="2" |T25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/nowiki>O|Growspan="2" ||ALT0|USDHC1_DATA7|-|ALT5|GPIO2_IO09|-| rowspan="3" |J1.154(eMMC on board)| rowspan="3" |NAND_DATA07| rowspan="3" |CPU.NAND_DATA07| rowspan="3" |M19| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA07|-|ALT1|QSPI_B_DATA3|-|ALT5|GPIO3_IO13
|-
|J5J1.24156(NAND on board)|I2C4_SCLNAND_RE_B|CPU.I2C4_SCLNAND_RE_B|F8K19
|NVCC_3V3
|I/O
|Internally used for NAND, do not connect
|
|
|-
|J5.25|I2C4_SDArowspan="3" |CPUJ1.I2C4_SDA|F9|NVCC_3V3|I/O156||(eMMC on board)|} ===Pinout Table JD5 pins declaration ==={| classrowspan="wikitable3" |NAND_RE_B! latexfontsize| rowspan="scriptsize3" | Pin CPU.NAND_RE_B! latexfontsize| rowspan="scriptsize3" | Pin NameK19! latexfontsize| rowspan="scriptsize3" | Internal Connections NVCC_3V3! latexfontsize| rowspan="scriptsize3" | BallI/pin # O! latexfontsize| rowspan="scriptsize3" |<nowiki> Voltage|ALT0|domain</nowiki>RAWNAND_RE_B! latexfontsize="scriptsize" | Type -! latexfontsize="scriptsize" | NotesALT1! latexfontsize="scriptsize" | Alternative FunctionsQSPI_B_DQS
|-
|JD5.1|DGND|DGND| -|<nowiki>-</nowiki>|G|ALT5|GPIO3_IO15
|-
|JD5J1.2158(NAND on board)|EEPROM_WPNAND_READY_B|Internal EEPROM Write ProtectCPU.NAND_READY_B| -K20
|NVCC_3V3
|I/O|Internally used for NAND, do not connect
|
|
|-
|JD5rowspan="2" |J1.3158(eMMC on board)| rowspan="2" |NCNAND_READY_B|Not Connectedrowspan="2" |CPU.NAND_READY_B| -rowspan="2" |K20| -rowspan="2" |NVCC_3V3|Zrowspan="2" |I/O| rowspan="2" ||ALT0|RAWNAND_READY_B
|-
|JD5.4|JTAG_TCK|CPU.JTAG_TCK|T5|NVCC_3V3|I|internal pull-up 10k to NVCC_3V3ALT5|GPIO3_IO16
|-
|JD5J1.5160(NAND on board)|JTAG_TMSNAND_WE_B|CPU.JTAG_TMSNAND_WE_B|V5K22
|NVCC_3V3
|I/O|Internally used for NAND, do not connect
|
|
|-
|JD5rowspan="2" |J1.6160(eMMC on board)|JTAG_TDOrowspan="2" |NAND_WE_B| rowspan="2" |CPU.JTAG_TDONAND_WE_B|U5rowspan="2" |K22| rowspan="2" |NVCC_3V3|rowspan="2" |I/O|rowspan="2" ||ALT0|RAWNAND_WE_B
|-
|JD5.7|JTAG_TDI|CPU.JTAG_TDI|W5|NVCC_3V3|I|ALT5|GPIO3_IO17
|-
|JD5J1.8162(NAND on board)|JTAG_nTRSTNAND_WP_B|CPU.JTAG_TRST_BNAND_WP_B|U6K21
|NVCC_3V3
|I/O|Internally used for NAND, do not connect
|
|
|-
|JD5rowspan="2" |J1.9162(eMMC on board)|CPU_PORnrowspan="2" |NAND_WP_B| rowspan="2" |CPU.POR_BNAND_WP_BPMIC.RESETMCU| rowspan="2" |K21|W203rowspan="2" |NVCC_3V3|NVCC_SNVSrowspan="2" |I/O|internal pullrowspan="2" ||ALT0|RAWNAND_WP_B|-up 100k to NVCC_SNVS|ALT5|GPIO3_IO18
|-
|JD5J1.10164|NVCC_3V3DGND|NVCC_3V3DGND
| -
|<nowiki>-</nowiki>
|SG||||-|J1.166|CLK1_N|CPU.CLK1_N|T23||D|
|
|
|-
|J1.168
|CLK1_P
|CPU.CLK1_P
|R23
|
|D
|
|
|
|-
|J1.170
|USB2_RXN
|CPU.USB2_RX_N
|B8
|
|D
|
|
|
|-
|J1.172
|USB2_RXP
|CPU.USB2_RX_P
|A8
|
|D
|
|
|
|-
|J1.174
|USB2_TXN
|CPU.USB2_TX_N
|B9
|
|D
|
|
|
|-
|J1.176
|USB2_TXP
|CPU.USB2_TX_P
|A9
|
|D
|
|
|
|-
|J1.178
|USB1_RXN
|CPU.USB1_RX_N
|B12
|
|D
|
|
|
|-
|J1.180
|USB1_RXP
|CPU.USB1_RX_P
|A12
|
|D
|
|
|
|-
|J1.182
|USB1_TXN
|CPU.USB1_TX_N
|B13
|
|D
|
|
|
|-
|J1.184
|USB1_TXP
|CPU.USB1_TX_P
|A13
|
|D
|
|
|
|-
|J1.186
|USB1_VBUS
|CPU.USB1_VBUS
|D14
| -
|S
|Absolute maximum ratings 5.25V
|
|
|-
|J1.188
|USB2_VBUS
|CPU.USB2_VBUS
|D9
| -
|S
|Absolute maximum ratings 5.25V
|
|
|-
|J1.190
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J1.192
|USB1_ID
|CPU.USB1_ID
|C14
|VDD_PHY_3V3
|I
|
|
|
|-
|J1.194
|USB2_ID
|CPU.USB2_ID
|C9
|VDD_PHY_3V3
|I
|
|
|
|-
|J1.196
|USB1_DN
|CPU.USB1_DN
|B14
| -
|D
|
|
|
|-
|J1.198
|USB1_DP
|CPU.USB1_DP
|A14
| -
|D
|
|
|
|-
|J1.200
|USB2_DP
|CPU.USB2_DP
|A10
| -
|D
|
|
|
|-
|J1.202
|USB2_DN
|CPU.USB2_DN
|B10
| -
|D
|
|
|
|-
|J1.204
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|}
 
==ONE PIECE J4 pins declaration ==
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" | Voltage domain
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
! colspan="2" |Alternative Functions
|-
|J4.1
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
| rowspan="7" |J4.2
| rowspan="7" |SAI1_RXD7
| rowspan="7" |CPU.SAI1_RXD7
| rowspan="7" |G1
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA7
|-
|ALT1
|SAI6_MCLK
|-
|ALT2
|SAI1_TX_SYNC
|-
|ALT3
|SAI1_TX_DATA4
|-
|ALT4
|CORESIGHT_TRACE7
|-
|ALT5
|GPIO4_IO09
|-
|ALT6
|SRC_BOOT_CFG7
|-
| rowspan="6" |J4.3
| rowspan="6" |SAI1_RXD6
| rowspan="6" |CPU.SAI1_RXD6
| rowspan="6" |G2
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA6
|-
|ALT1
|SAI6_TX_SYNC
|-
|ALT2
|SAI6_RX_SYNC
|-
|ALT4
|CORESIGHT_TRACE6
|-
|ALT5
|GPIO4_IO08
|-
|ALT6
|SRC_BOOT_CFG6
|-
| rowspan="7" |J4.4
| rowspan="7" |SAI1_RXD5
| rowspan="7" |CPU.SAI1_RXD5
| rowspan="7" |F1
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA5
|-
|ALT1
|SAI6_TX_DATA0
|-
|ALT2
|SAI6_RX_DATA0
|-
|ALT3
|SAI1_RX_SYNC
|-
|ALT4
|CORESIGHT_TRACE5
|-
|ALT5
|GPIO4_IO07
|-
|ALT6
|SRC_BOOT_CFG5
|-
| rowspan="6" |J4.5
| rowspan="6" |SAI1_RXD4
| rowspan="6" |CPU.SAI1_RXD4
| rowspan="6" |J1
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA4
|-
|ALT1
|SAI6_TX_BCLK
|-
|ALT2
|SAI6_RX_BCLK
|-
|ALT4
|CORESIGHT_TRACE4
|-
|ALT5
|GPIO4_IO06
|-
|ALT6
|SRC_BOOT_CFG4
|-
| rowspan="5" |J4.6
| rowspan="5" |SAI1_RXD3
| rowspan="5" |CPU.SAI1_RXD3
| rowspan="5" |J2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA3
|-
|ALT1
|SAI5_RX_DATA3
|-
|ALT4
|CORESIGHT_TRACE3
|-
|ALT5
|GPIO4_IO05
|-
|ALT6
|SRC_BOOT_CFG3
|-
| rowspan="5" |J4.7
| rowspan="5" |SAI1_RXD2
| rowspan="5" |CPU.SAI1_RXD2
| rowspan="5" |H2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA2
|-
|ALT1
|SAI5_RX_DATA2
|-
|ALT4
|CORESIGHT_TRACE2
|-
|ALT5
|GPIO4_IO04
|-
|ALT6
|SRC_BOOT_CFG2
|-
| rowspan="5" |J4.8
| rowspan="5" |SAI1_RXD1
| rowspan="5" |CPU.SAI1_RXD1
| rowspan="5" |L2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA1
|-
|ALT1
|SAI5_RX_DATA1
|-
|ALT4
|CORESIGHT_TRACE1
|-
|ALT5
|GPIO4_IO03
|-
|ALT6
|SRC_BOOT_CFG1
|-
| rowspan="5" |J4.9
| rowspan="5" |SAI1_RXD0
| rowspan="5" |CPU.SAI1_RXD0
| rowspan="5" |K2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA0
|-
|ALT1
|SAI5_RX_DATA0
|-
|ALT4
|CORESIGHT_TRACE0
|-
|ALT5
|GPIO4_IO02
|-
|ALT6
|SRC_BOOT_CFG0
|-
| rowspan="4" |J4.10
| rowspan="4" |SAI1_RXC
| rowspan="4" |CPU.SAI1_RXC
| rowspan="4" |K1
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_RX_BCLK
|-
|ALT1
|SAI5_RX_BCLK
|-
|ALT4
|CORESIGHT_TRACE_CTL
|-
|ALT5
|GPIO4_IO01
|-
| rowspan="4" |J4.11
| rowspan="4" |SAI1_RXFS
| rowspan="4" |CPU.SAI1_RXFS
| rowspan="4" |L1
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_RX_SYNC
|-
|ALT1
|SAI5_RX_SYNC
|-
|ALT4
|CORESIGHT_TRACE_CLK
|-
|ALT5
|GPIO4_IO00
|-
|J4.12
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
| rowspan="4" |J4.13
| rowspan="4" |SAI1_MCLK
| rowspan="4" |CPU.SAI1_MCLK
| rowspan="4" |
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_MCLK
|-
|ALT1
|SAI5_MCLK
|-
|ALT2
|SAI1_TX_BCLK
|-
|ALT5
|GPIO4_IO20
|-
|J4.14
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
| rowspan="4" |J4.15
| rowspan="4" |SAI1_TXFS
| rowspan="4" |CPU.SAI1_TXFS
| rowspan="4" |H4
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_TX_SYNC
|-
|ALT1
|SAI5_TX_SYNC
|-
|ALT4
|CORESIGHT_EVENTO
|-
|ALT5
|GPIO4_IO10
|-
| rowspan="4" |J4.16
| rowspan="4" |SAI1_TXC
| rowspan="4" |CPU.SAI1_TXC
| rowspan="4" |J5
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_TX_BCLK
|-
|ALT1
|SAI5_TX_BCLK
|-
|ALT4
|CORESIGHT_EVENTI
|-
|ALT5
|GPIO4_IO11
|-
| rowspan="5" |J4.17
| rowspan="5" |SAI1_TXD0
| rowspan="5" |CPU.SAI1_TXD0
| rowspan="5" |F2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA0
|-
|ALT1
|SAI5_TX_DATA0
|-
|ALT4
|CORESIGHT_TRACE8
|-
|ALT5
|GPIO4_IO12
|-
|ALT6
|SRC_BOOT_CFG8
|-
| rowspan="5" |J4.18
| rowspan="5" |SAI1_TXD1
| rowspan="5" |CPU.SAI1_TXD1
| rowspan="5" |E2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA1
|-
|ALT1
|SAI5_TX_DATA1
|-
|ALT4
|CORESIGHT_TRACE9
|-
|ALT5
|GPIO4_IO13
|-
|ALT6
|SRC_BOOT_CFG9
|-
| rowspan="5" |J4.19
| rowspan="5" |SAI1_TXD2
| rowspan="5" |CPU.SAI1_TXD2
| rowspan="5" |B2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA2
|-
|ALT1
|SAI5_TX_DATA2
|-
|ALT4
|CORESIGHT_TRACE10
|-
|ALT5
|GPIO4_IO14
|-
|ALT6
|SRC_BOOT_CFG10
|-
| rowspan="5" |J4.20
| rowspan="5" |SAI1_TXD3
| rowspan="5" |CPU.SAI1_TXD3
| rowspan="5" |D1
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA3
|-
|ALT1
|SAI5_TX_DATA3
|-
|ALT4
|CORESIGHT_TRACE11
|-
|ALT5
|GPIO4_IO15
|-
|ALT6
|SRC_BOOT_CFG11
|-
| rowspan="6" |J4.21
| rowspan="6" |SAI1_TXD4
| rowspan="6" |CPU.SAI1_TXD4
| rowspan="6" |D2
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA4
|-
|ALT1
|SAI6_RX_BCLK
|-
|ALT2
|SAI6_TX_BCLK
|-
|ALT4
|CORESIGHT_TRACE12
|-
|ALT5
|GPIO4_IO16
|-
|ALT6
|SRC_BOOT_CFG12
|-
| rowspan="6" |J4.22
| rowspan="6" |SAI1_TXD5
| rowspan="6" |CPU.SAI1_TXD5
| rowspan="6" |C2
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA5
|-
|ALT1
|SAI6_RX_DATA0
|-
|ALT2
|SAI6_TX_DATA0
|-
|ALT4
|CORESIGHT_TRACE13
|-
|ALT5
|GPIO4_IO17
|-
|ALT6
|SRC_BOOT_CFG13
|-
| rowspan="6" |J4.23
| rowspan="6" |SAI1_TXD6
| rowspan="6" |CPU.SAI1_TXD6
| rowspan="6" |B3
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA6
|-
|ALT1
|SAI6_RX_SYNC
|-
|ALT2
|SAI6_TX_SYNC
|-
|ALT4
|CORESIGHT_TRACE14
|-
|ALT5
|GPIO4_IO18
|-
|ALT6
|SRC_BOOT_CFG14
|-
| rowspan="5" |J4.24
| rowspan="5" |SAI1_TXD7
| rowspan="5" |CPU.SAI1_TXD7
| rowspan="5" |C1
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA7
|-
|ALT1
|SAI6_MCLK
|-
|ALT4
|CORESIGHT_TRACE15
|-
|ALT5
|GPIO4_IO19
|-
|ALT6
|SRC_BOOT_CFG15
|-
|J4.25
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|}
 
==ONE PIECE J5 pins declaration ==
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" | Voltage domain
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
! colspan="2" |Alternative Functions
|-
|J5.1
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.2
|PCIE2_RXN
|CPU.PCIE2_RXN_N
|D24
| -
|D
|
|
|
|-
|J5.3
|PCIE2_RXP
|CPU.PCIE2_RXN_P
|D25
| -
|D
|
|
|
|-
|J5.4
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.5
|PCIE2_TXN
|CPU.PCIE2_TXN_N
|E24
| -
|D
|
|
|
|-
|J5.6
|PCIE2_TXP
|CPU.PCIE2_TXN_P
|E25
| -
|D
|
|
|
|-
|J5.7
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.8
|PCIE2_REF_CLKN
|CPU.PCIE2_REF_PAD_CLK_N
|F24
| -
|D
|
|
|
|-
|J5.9
|PCIE2_REF_CLKP
|CPU.PCIE2_REF_PAD_CLK_P
|F25
| -
|D
|
|
|
|-
|J5.10
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.11
|CSI_P2_CKN
|CPU.MIPI_CSI2_CLK_N
|A19
| -
|D
|
|
|
|-
|J5.12
|CSI_P2_CKP
|CPU.MIPI_CSI2_CLK_P
|B19
| -
|D
|
|
|
|-
|J5.13
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.14
|CSI_P2_DN0
|CPU.MIPI_CSI2_D0_N
|C20
| -
|D
|
|
|
|-
|J5.15
|CSI_P2_DP0
|CPU.MIPI_CSI2_D0_P
|D10
| -
|D
|
|
|
|-
|J5.16
|CSI_P2_DN1
|CPU.MIPI_CSI2_D1_N
|A20
| -
|D
|
|
|
|-
|J5.17
|CSI_P2_DP1
|CPU.MIPI_CSI2_D1_P
|B20
| -
|D
|
|
|
|-
|J5.18
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.19
|CSI_P2_DN2
|CPU.MIPI_CSI2_D2_N
|A21
| -
|D
|
|
|
|-
|J5.20
|CSI_P2_DP2
|CPU.MIPI_CSI2_D2_P
|B21
| -
|D
|
|
|
|-
|J5.21
|CSI_P2_DN3
|CPU.MIPI_CSI2_D3_N
|C19
| -
|D
|
|
|
|-
|J5.22
|CSI_P2_DP3
|CPU.MIPI_CSI2_D3_P
|D19
| -
|D
|
|
|
|-
|J5.23
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
| rowspan="4" |J5.24
| rowspan="4" |I2C4_SCL
| rowspan="4" |CPU.I2C4_SCL
| rowspan="4" |F8
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|I2C4_SCL
|-
|ALT1
|PWM2_OUT
|-
|ALT2
|PCIE1_CLKREQ_B
|-
|ALT5
|GPIO5_IO20
|-
| rowspan="4" |J5.25
| rowspan="4" |I2C4_SDA
| rowspan="4" |CPU.I2C4_SDA
| rowspan="4" |F9
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|I2C4_SDA
|-
|ALT1
|PWM1_OUT
|-
|ALT2
|PCIE2_CLKREQ_B
|-
|ALT5
|GPIO5_IO21
|}
U0007
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Retrieved from "https://wiki.dave.eu/index.php/Special:MobileDiff/10235...19065"