Open main menu

DAVE Developer's Wiki β

Changes

MITO 8M SOM/MITO 8M Hardware/Pinout Table

35,890 bytes added, 17:49, 28 December 2023
no edit summary
<section begin="History" />
{| style="border-collapse:collapse; "
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
|-
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0{{oldid| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" 10368|Sep 2020/09/29}}
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |2021/02/02
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |Add pull-up/down information
|-
|}
<section end="History" /><section begin="Body" />==Connectors and Pinout Table=====Introduction=description==
This chapter contains === Connectors description ===In the following table are described all available connectors integrated on MITO 8M SOM:{| class="wikitable"|-!Connector name!Connector Type!Notes!Carrier board counterpart|-|J1|SODIMM edge connector 204 pin|partially compatible with [[AXEL Lite SOM]]|TE Connectivity 2-2013289-1|-|J4|ONE PIECE connector single row 25pins||SAMTEC FSI-125-03-G-S-AD-TR|-|J5|ONE PIECE connector single row 25pins||SAMTEC FSI-125-03-G-S-AD-TR|}The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to MITO 8M pinout specifications. See the images below for reference: [[File:MITO 8M-conn-TOP.png|500px|thumb|MITO 8M TOP view|none]][[File:MITO 8M-conn-BOTTOM.png|500px|thumb|MITO 8M BOTTOM view|none]] Below a detailed description of the MITO 8M modulepinout, grouped in the following tables:* two tables (odd ODD and even EVEN pins) that report the pin mapping of the 204-pin SO-DIMM MITO 8M edge* a dedicated tables for J4 one-piece connector* a dedicated tables for J5 one-piece connector.
=== Pinout Table description ===
Each row in the pinout tables contains the following information:
 {| class="wikitable" style="width:50%;"
|-
|'''Pin'''
|-
|'''Pin Name'''
| Pin (signal) name on the AxelLite MITO 8M connectors
|-
|'''Internal<br>connections'''
| Connections to the Axel Ultra components
* CPU.<x> : pin connected to CPU pad named <x>
* CAN.<x> : pin connected to the CAN transceiver* PMIC.<x> : pin connected to the Power Manager IC(NXP PF4210)* LAN.<x> : pin connected to the LAN PHY(MICROCHIP KSZ9031RNX)* NORBRIDGE.<x> : pin connected to the flash NOR* SV.<x>: pin connected to voltage supervisor* MTR: pin connected MIPI-to voltage monitors-LVDS bridge (TI SN65DSI84)
|-
|'''Ball/pin #'''
|}
===Pinout Table SODIMM J1 ODD pins declaration ===
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
! colspan="2" latexfontsize="scriptsize" | Alternative Functions
|-
|J1.1
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|3.3VIN
|S
|
|
|
|3.3VIN
|S
|
|
|
|3.3VIN
|S
|
|
|
|3.3VIN
|S
|
|
|
| -
|G
|
|
|
|NVCC_1V8
|I/O
|must Must be level translated if used @ 3V3Internally pulled-up to 1.8V during bootstrap|
|
|-
|NVCC_1V8
|I/O
|must Must be level translated if used @ 3V3Internally pulled-up to 1.8V during bootstrap|
|
|-
| -
|G
|
|
|
| -
|D
|
|
|
| -
|D
|
|
|
| -
|D
|
|
|
| -
|D
|
|
|
| -
|D
|
|
|
| -
|D
|
|
|
| -
|D
|
|
|
| -
|D
|
|
|
| -
|G
|
|
|
|-
| rowspan="4" |J1.37| rowspan="4" |GPIO1_IO00| rowspan="4" |CPU.GPIO1_IO00| rowspan="4" |T6| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0
|GPIO1_IO00
|
|
|
|
|
|
|-
|ALT1|CCM_ENET_PHY_REF_CLK_ROOT|-|ALT5|ANAMIX_REF_CLK_32K|-|ALT6|CCM_EXT_CLK1|-| rowspan="4" |J1.39| rowspan="4" |GPIO1_IO01| rowspan="4" |CPU.GPIO1_IO01| rowspan="4" |T7| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" |Internally used for ETH PHY reset, do not connect|ALT0|GPIO1_IO01|-|ALT1|PWM1_OUT|-|ALT5|ANAMIX_REF_CLK_25M|-|ALT6|CCM_EXT_CLK2|-| rowspan="3" |J1.41| rowspan="3" |SPDIF_EXT_CLK| rowspan="3" |CPU.SPDIF_EXT_CLK| rowspan="3" |E6| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SPDIF1_EXT_CLK|-|ALT1|PWM1_OUT|-|ALT5|GPIO5_IO05|-| rowspan="3" |J1.43| rowspan="3" |GPIO1_IO13| rowspan="3" |CPU.GPIO1_IO13| rowspan="3" |K6| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" |Internally used, do not connect|ALT0|GPIO1_IO13|-|ALT1|USB1_OTG_OC|-|ALT5|PWM2_OUT|-|J1.45|VDD_PHY_1V8
|
|
|
|-
| rowspan="3" |J1.47| rowspan="3" |ECSPI2_SCLK| rowspan="3" |CPU.ECSPI2_SCLK| rowspan="3" |C5| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|ECSPI2_SCLK|-|ALT1|UART4_RX|-|ALT5|GPIO5_IO10|-| rowspan="3" |J1.49| rowspan="3" |ECSPI2_MOSI| rowspan="3" |CPU.ECSPI2_MOSI| rowspan="3" |E5| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|ECSPI2_MOSI|-|ALT1|UART4_TX|-|ALT5|GPIO5_IO11|-| rowspan="3" |J1.51| rowspan="3" |GPIO1_IO08| rowspan="3" |CPU.GPIO1_IO08| rowspan="3" |N7| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|GPIO1_IO08|-|ALT1|ENET1_1588_EVENT0_IN|-|ALT5|USDHC2_RESET_B|-| rowspan="3" |J1.53| rowspan="3" |GPIO1_IO09| rowspan="3" |CPU.GPIO1_IO09| rowspan="3" |M7| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|GPIO1_IO09|-|ALT1|ENET1_1588_EVENT0_OUT|-|ALT5|SDMA2_EXT_EVENT0|-| rowspan="3" |J1.4155| rowspan="3" |ECSPI2_MISO| rowspan="3" |CPU.ECSPI2_MISO| rowspan="3" |B5| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|ECSPI2_MISO|-|ALT1|UART4_CTS_B|-|ALT5|GPIO5_IO12|-|J1.57|DGND |DGND|-|-|G
|
|
|
|-
| rowspan="3" |J1.4359|rowspan="3" |ECSPI2_SS0| rowspan="3" |CPU.ECSPI2_SS0|rowspan="3" |A5|rowspan="3" |NVCC_3V3|rowspan="3" |I/O| rowspan="3" ||ALT0|ECSPI2_SS0
|-
|J1.45||||||ALT1|UART4_RTS_B
|-
|J1.47||||||ALT5|GPIO5_IO13
|-
| rowspan="3" |J1.4961|rowspan="3" |GPIO1_IO05|rowspan="3" |CPU.GPIO1_IO05|rowspan="3" |P7|rowspan="3" |NVCC_3V3|rowspan="3" |I/O| rowspan="3" |Internally used for MIPI-to-LVDS interrupt, do not connectPulled-up to NVCC_3V3|ALT0|GPIO1_IO05
|-
|J1.51||||||ALT1|M4_NMI
|-
|ALT5|CCM_PMIC_READY|-| rowspan="3" |J1.63| rowspan="3" |I2C2_SCL| rowspan="3" |CPU.I2C2_SCL| rowspan="3" |G7| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|I2C2_SCL|-|ALT1|ENET1_1588_EVENT1_IN|-|ALT5|GPIO5_IO16|-| rowspan="3" |J1.65| rowspan="3" |I2C2_SDA| rowspan="3" |CPU.I2C2_SDA| rowspan="3" |F7| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|I2C2_SDA|-|ALT1|ENET1_1588_EVENT1_OUT|-|ALT5|GPIO5_IO17|-| rowspan="4" |J1.67| rowspan="4" |GPIO1_IO06| rowspan="4" |CPU.GPIO1_IO06| rowspan="4" |N5| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" |Internally used for MIPI-to-LVDS enable, do not connect|ALT0|GPIO1_IO06|-|ALT1|ENET1_MDC|-|ALT5|USDHC1_CD_B|-|ALT6|CCM_EXT_CLK3|-| rowspan="3" |J1.69| rowspan="3" |SAI2_RXC| rowspan="3" |CPU.SAI2_RXC| rowspan="3" |H3| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SAI2_RX_BCLK|-|ALT1|SAI5_TX_BCLK|-|ALT5|GPIO4_IO22|-| rowspan="3" |J1.71| rowspan="3" |SAI2_RXFS| rowspan="3" |CPU.SAI2_RXFS| rowspan="3" |J4| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SAI2_RX_SYNC|-|ALT1|SAI5_TX_SYNC|-|ALT5|GPIO4_IO21|-|J1.5373|DGND |DGND|-|-|G
|
|
|
|-
| rowspan="2" |J1.75| rowspan="2" |SD2_DATA0| rowspan="2" |CPU.SD2_DATA0| rowspan="2" |N22| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC2_DATA0|-|ALT5|GPIO2_IO15|-| rowspan="2" |J1.77| rowspan="2" |SD2_DATA1| rowspan="2" |CPU.SD2_DATA1| rowspan="2" |N21| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC2_DATA1|-|ALT5|GPIO2_IO16|-| rowspan="2" |J1.79| rowspan="2" |SD2_DATA2| rowspan="2" |CPU.SD2_DATA2| rowspan="2" |P22| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC2_DATA2|-|ALT5|GPIO2_IO17|-| rowspan="2" |J1.5581| rowspan="2" |SD2_DATA3| rowspan="2" |CPU.SD2_DATA03| rowspan="2" |P21| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC2_DATA3|-|ALT5|GPIO2_IO18|-| rowspan="2" |J1.83| rowspan="2" |SD2_CMD| rowspan="2" |CPU.SD2_CMD| rowspan="2" |M22| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC2_CMD|-|ALT5|GPIO2_IO14|-| rowspan="2" |J1.85| rowspan="2" |SD2_CLK| rowspan="2" |CPU.SD2_CLK| rowspan="2" |L22| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC2_CLK|-|ALT5|GPIO2_IO13|-|J1.87|DGND |DGND|-|-|G
|
|
|
|-
| rowspan="3" |J1.5789|rowspan="3" |UART3_TXD| rowspan="3" |CPU.UART3_TXD|rowspan="3" |B7|rowspan="3" |NVCC_3V3|rowspan="3" |I/O| rowspan="3" ||ALT0|UART3_TX
|-
|ALT1|UART1_RTS_B|-|ALT5|GPIO5_IO27|-| rowspan="3" |J1.91| rowspan="3" |UART3_RXD| rowspan="3" |CPU.UART3_RXD| rowspan="3" |A6| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|UART3_RX|-|ALT1|UART1_CTS_B|-|ALT5|GPIO5_IO26|-| rowspan="4" |J1.93| rowspan="4" |UART4_TXD| rowspan="4" |CPU.UART4_TXD| rowspan="4" |D7| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|UART4_TX|-|ALT1|UART2_RTS_B|-|ALT2|PCIE2_CLKREQ_B|-|ALT5|GPIO5_IO29|-| rowspan="4" |J1.5995| rowspan="4" |UART4_RXD| rowspan="4" |CPU.UART4_RXD| rowspan="4" |C6| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|UART4_RX|-|ALT1|UART2_CTS_B|-|ALT2|PCIE1_CLKREQ_B|-|ALT5|GPIO5_IO28|-| rowspan="2" |J1.97| rowspan="2" |SD2_WP| rowspan="2" |CPU.SD2_WP| rowspan="2" |M21| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC2_WP|-|ALT5|GPIO2_IO20|-| rowspan="2" |J1.99| rowspan="2" |SD2_RST_B| rowspan="2" |CPU.SD2_RESET_B| rowspan="2" |R22| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC2_RESET_B|-|ALT5|GPIO2_IO19|-|J1.101|HDMI_DDC_SCL|CPU.HDMI_DDC_SCL|R3|VDD_PHY_1V8|I/O
|
|
|
|-
|J1.103
|HDMI_DDC_SDA
|CPU.HDMI_DDC_SDA
|P3
|VDD_PHY_1V8
|I/O
|
|
|
|-
|J1.61105|HDMI_AUX_N|CPU.HDMI_AUX_N|V2| -|D|connected with capacitor in series
|
|
|-
|J1.107
|HDMI_AUX_P
|CPU.HDMI_AUX_P
|V1
| -
|D
|connected with capacitor in series
|
|
|-
|J1.63109|DGND |DGND| -| -|G
|
|
|
|-
|J1.111
|HDMI_TX_M_LN_3
|CPU.HDMI_TX_M_LN_3
|M2
| -
|D
|connected with capacitor in series
|
|
|-
|J1.113
|HDMI_TX_P_LN_3
|CPU.HDMI_TX_P_LN_3
|M1
| -
|D
|connected with capacitor in series
|
|
|-
|J1.65115|HDMI_TX_M_LN_0|CPU.HDMI_TX_M_LN_0|T2| -|D|connected with capacitor in series
|
|
|-
|J1.117
|HDMI_TX_P_LN_0
|CPU.HDMI_TX_P_LN_0
|T1
| -
|D
|connected with capacitor in series
|
|
|-
|J1.119
|HDMI_TX_M_LN_1
|CPU.HDMI_TX_M_LN_1
|U1
| -
|D
|connected with capacitor in series
|
|
|-
|J1.67121|HDMI_TX_P_LN_1|CPU.HDMI_TX_P_LN_1|U2| -|D|connected with capacitor in series
|
|
|-
|J1.123
|HDMI_TX_M_LN_2
|CPU.HDMI_TX_M_LN_2
|N1
| -
|D
|connected with capacitor in series
|
|
|-
|J1.125
|HDMI_TX_P_LN_2
|CPU.HDMI_TX_P_LN_2
|N2
| -
|D
|connected with capacitor in series
|
|
|-
|J1.69127|HDMI_CEC|CPU.HDMI_CEC|W3|VDD_PHY_1V8|I/O
|
|
|
|-
|J1.129
|HDMI_HPD
|CPU.HDMI_HPD
|W2
|VDD_PHY_1V8
|I/O
|
|
|
|-
|J1.71131|DGND |DGND| -| -|G
|
|
|
|-
|J1.133
|LVDS0_CLK_N
|BRIDGE.A_CLKN
|F9
| -
|D
|
|
|
|-
|J1.73135|LVDS0_CLK_P|BRIDGE.A_CLKP|F8| -|D
|
|
|
|-
|J1.137
|LVDS0_TX0_N
|BRIDGE.A_Y0N
|C9
| -
|D
|
|
|
|-
|J1.75139|LVDS0_TX0_P|BRIDGE.A_Y0P|C8| -|D
|
|
|
|-
|J1.141
|LVDS0_TX1_N
|BRIDGE.A_Y1N
|D9
| -
|D
|
|
|
|-
|J1.77143|LVDS0_TX1_P|BRIDGE.A_Y1P|D8| -|D
|
|
|
|-
|J1.145
|LVDS0_TX2_N
|BRIDGE.A_Y2N
|E9
| -
|D
|
|
|
|-
|J1.79147|LVDS0_TX2_P|BRIDGE.A_Y2P|E8| -|D
|
|
|
|-
|J1.149
|LVDS0_TX3_N
|BRIDGE.A_Y3N
|G9
| -
|D
|
|
|
|-
|J1.81151|LVDS0_TX3_P|BRIDGE.A_Y3P|G8| -|D
|
|
|
|-
|J1.153
|DGND
|DGND
| -
| -
|G
|
|
|
|-
|J1.83155|LVDS1_CLK_N|BRIDGE.B_CLKN|A6| -|D
|
|
|
|-
|J1.157
|LVDS1_CLK_P
|BRIDGE.B_CLKP
|B6
| -
|D
|
|
|
|-
|J1.85159|LVDS1_TX0_N|BRIDGE.B_Y0N|A3| -|D
|
|
|
|-
|J1.161
|LVDS1_TX0_P
|BRIDGE.B_Y0P
|B3
| -
|D
|
|
|
|-
|J1.87163|LVDS1_TX1_N|BRIDGE.B_Y1N|A4| -|D
|
|
|
|-
|J1.165
|LVDS1_TX1_P
|BRIDGE.B_Y1P
|B4
| -
|D
|
|
|
|-
|J1.89167|LVDS1_TX2_N|BRIDGE.B_Y2N|A5| -|D
|
|
|
|-
|J1.169
|LVDS1_TX2_P
|BRIDGE.B_Y2P
|B5
| -
|D
|
|
|
|-
|J1.91171|LVDS1_TX3_N|BRIDGE.B_Y3N|A7| -|D
|
|
|
|-
|J1.173
|LVDS1_TX3_P
|BRIDGE.B_Y3P
|B7
| -
|D
|
|
|
|-
|J1.93175|DGND |DGND|-|-|G
|
|
|
|-
| rowspan="2" |J1.177| rowspan="2" |SD2_CD_B| rowspan="2" |CPU.SD2_CD_B| rowspan="2" |L21| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC2_CD_B|-|ALT5|GPIO2_IO12|-| rowspan="3" |J1.95179|rowspan="3" |ECSPI1_SS0|rowspan="3" |CPU.ECSPI1_SS0|rowspan="3" |D4|rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|ECSPI1_SS0
|-
|J1.97||||||ALT1|UART3_RTS_B
|-
|ALT5|GPIO5_IO09|-| rowspan="3" |J1.181| rowspan="3" |ECSPI1_SCLK| rowspan="3" |CPU.ECSPI1_SCLK| rowspan="3" |D5| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|ECSPI1_SCLK|-|ALT1|UART3_RX|-|ALT5|GPIO5_IO06|-| rowspan="3" |J1.99183| rowspan="3" |ECSPI1_MISO|rowspan="3" |CPU.ECSPI1_MISO|rowspan="3" |B4|rowspan="3" |NVCC_3V3|rowspan="3" |I/O| rowspan="3" ||ALT0|ECSPI1_MISO
|-
|J1.101||||||ALT1|UART3_CTS_B
|-
|J1.103||||||ALT5|GPIO5_IO08
|-
| rowspan="3" |J1.185| rowspan="3" |GPIO1_IO03| rowspan="3" |CPU.GPIO1_IO03| rowspan="3" |P4| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|GPIO1_IO03|-|ALT1|USDHC1_VSELECT|-|ALT5|SDMA1_EXT_EVENT0|-| rowspan="3" |J1.105187|rowspan="3" |UART2_TXD|rowspan="3" |CPU.UART2_TXD| rowspan="3" |D6| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" |used as default Linux console|ALT0|UART2_TX|-|ALT1|ECSPI3_SS0
|-
|J1.107||||||ALT5|GPIO5_IO25
|-
| rowspan="3" |J1.109189|rowspan="3" |UART2_RXD| rowspan="3" |CPU.UART2_RXD|rowspan="3" |B6|rowspan="3" |NVCC_3V3|rowspan="3" |I/O|rowspan="3" |used as default Linux console|ALT0|UART2_RXD
|-
|ALT1|ECSPI3_MISO|-|ALT5|GPIO5_IO24|-| rowspan="3" |J1.191| rowspan="3" |UART1_TXD| rowspan="3" |CPU.UART1_TXD| rowspan="3" |A7| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|UART1_TX|-|ALT1|ECSPI3_MOSI|-|ALT5|GPIO5_IO23|-| rowspan="3" |J1.193| rowspan="3" |UART1_RXD| rowspan="3" |CPU.UART1_RXD| rowspan="3" |C7| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|UART1_RXD|-|ALT1|ECSPI3_SCLK|-|ALT5|GPIO5_IO22|-| rowspan="3" |J1.195| rowspan="3" |ECSPI1_MOSI| rowspan="3" |CPU.ECSPI1_MOSI| rowspan="3" |A4| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|ECSPI1_MOSI|-|ALT1|UART3_TX|-|ALT5|GPIO5_IO07|-| rowspan="4" |J1.197| rowspan="4" |GPIO1_IO14| rowspan="4" |CPU.GPIO1_IO14| rowspan="4" |K7| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|GPIO1_IO14|-|ALT1|USB2_OTG_PWR|-|ALT5|PWM3_OUT|-|ALT6|CCM_CLKO1|-| rowspan="3" |J1.199| rowspan="3" |GPIO1_IO04| rowspan="3" |CPU.GPIO1_IO04| rowspan="3" |P5| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|GPIO1_IO04|-|ALT1|USDHC2_VSELECT|-|ALT5|SDMA1_EXT_EVENT1|-| rowspan="3" |J1.201| rowspan="3" |GPIO1_IO12| rowspan="3" |CPU.GPIO1_IO12| rowspan="3" |L7| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|GPIO1_IO12|-|ALT1|USB1_OTG_PWR|-|ALT5|SDMA2_EXT_EVENT1|-|J1.111203|DGND |DGND|-|-|G
|
|
|
|-
|} ==SODIMM J1 EVEN pins declaration == {| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" | Voltage domain ! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! colspan="2" latexfontsize="scriptsize" | Alternative Functions|-|J1.1132|DGND|DGND| -|<nowiki>-</nowiki>|G
|
|
|
|-
|J1.4
|3.3VIN
|INPUT VOLTAGE
| -
|3.3VIN
|S
|
|
|
|-
|J1.1156|3.3VIN |INPUT VOLTAGE| -|3.3VIN|S
|
|
|
|-
|J1.8
|3.3VIN
|INPUT VOLTAGE
| -
|3.3VIN
|S
|
|
|
|-
|J1.11710|3.3VIN |INPUT VOLTAGE| -|3.3VIN|S
|
|
|
|-
|J1.12
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J1.11914|PMIC_LICELL |PMIC.LICELL|30| -|S
|
|
|
|-
|J1.16
|CPU_ONOFF
|CPU.ONOFF
|W21
|NVCC_SNVS
|I
|internal pull-up 100k to NVCC_SNVS
|
|
|-
|J1.12118|BOARD_PGOOD| -| -|NVCC_3V3|O
|
|
|
|-
|J1.20
|BOOT_MODE_SEL
|BOOT MODE SELECTION
| -
|NVCC_3V3
|I
|internal pull-up to NVCC_3V3
|
|
|-
|J1.22
|CPU_PORn
|CPU.POR_B
PMIC.RESETMCU
|W20
3
|NVCC_SNVS
|I/O
|internal pull-up 100k to NVCC_SNVS
|
|
|-
|J1.12324|EXT_RESET|MASTER RESET|-|-|I|internal pull-up to NVCC_SNVS
|
|
|-
| rowspan="4" |J1.26| rowspan="4" |SAI3_RXC| rowspan="4" |CPU.SAI3_RXC| rowspan="4" |F4| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI3_RX_BCLK|-|ALT1|GPT1_CAPTURE2|-|ALT2|SAI5_RX_BCLK|-|ALT5|GPIO4_IO29|-| rowspan="4" |J1.12528| rowspan="4" |GPIO1_IO02| rowspan="4" |CPU.GPIO1_IO02| rowspan="4" |R4| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" |Internally used for SW reset, do not connect|ALT0|GPIO1_IO02|-|ALT1|WDOG1_WDOG_B|-|ALT5|WDOG1_WDOG_ANY|-|ALT7|SJC_DE_B|-|J1.30|DGND|DGND|-|<nowiki>-</nowiki>|G
|
|
|
|-
| rowspan="4" |J1.12732| rowspan="4" |SAI3_RXD| rowspan="4" |CPU.SAI3_RXD| rowspan="4" |F3| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI3_RX_DATA0|-|ALT1|GPT1_COMPARE1|-|ALT2|SAI5_RX_DATA0
|-
|ALT5|GPIO4_IO30|-| rowspan="3" |J1.34| rowspan="3" |SAI2_MCLK| rowspan="3" |CPU.SAI2_MCLK| rowspan="3" |H5| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SAI2_MCLK|-|ALT1|SAI5_MCLK|-|ALT5|GPIO4_IO27|-| rowspan="4" |J1.12936| rowspan="4" |SAI3_RXFS|rowspan="4" |CPU.SAI3_RXFS|rowspan="4" |G4|rowspan="4" |NVCC_3V3|rowspan="4" |I/O| rowspan="4" ||ALT0|SAI3_RX_SYNC
|-
|J1.131||||||ALT1|GPT1_CAPTURE1
|-
|J1.133||||||ALT2|SAI5_RX_SYNC
|-
|ALT5|GPIO4_IO28|-| rowspan="4" |J1.13538| rowspan="4" |I2C3_SCL| rowspan="4" |CPU.I2C3_SCL| rowspan="4" |G8| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|I2C3_SCL|-|ALT1|PWM4_OUT|-|ALT2|GPT2_CLK|-|ALT5|GPIO5_IO18
|-
| rowspan="4" |J1.13740|rowspan="4" |SAI3_TXFS| rowspan="4" |CPU.SAI3_TXFS|rowspan="4" |G3|rowspan="4" |NVCC_3V3|rowspan="4" |I/O| rowspan="4" ||ALT0|SAI3_TX_SYNC
|-
|J1.139||||||ALT1|GPT1_CLK
|-
|ALT2|SAI5_RX_DATA1|-|ALT5|GPIO4_IO31|-| rowspan="3" |J1.14142| rowspan="3" |SPDIF_RX| rowspan="3" |CPU.SPDIF_RX| rowspan="3" |G6| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SPDIF1_IN|-|ALT1|PWM2_OUT|-|ALT5|GPIO5_IO04
|-
| rowspan="3" |J1.14344|rowspan="3" |SPDIF_TX| rowspan="3" |CPU.SPDIF_TX|rowspan="3" |F6|rowspan="3" |NVCC_3V3|rowspan="3" |I/O| rowspan="3" ||ALT0|SPDIF1_OUT
|-
|J1.145||||||ALT1|PWM3_OUT
|-
|ALT5|GPIO5_IO03|-| rowspan="4" |J1.46| rowspan="4" |SAI3_MCLK| rowspan="4" |CPU.SAI3_MCLK| rowspan="4" |D3| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI3_MCLK|-|ALT1|PWM4_OUT|-|ALT2|SAI5_MCLK|-|ALT5|GPIO5_IO02|-| rowspan="4" |J1.48| rowspan="4" |I2C3_SDA| rowspan="4" |CPU.I2C3_SDA| rowspan="4" |E9| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|I2C3_SDA|-|ALT1|PWM3_OUT|-|ALT2|GPT3_CLK|-|ALT5|GPIO5_IO19|-| rowspan="4" |J1.50| rowspan="4" |SAI3_TXC| rowspan="4" |CPU.SAI3_TXC| rowspan="4" |C4| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI3_TX_BCLK|-|ALT1|GPT1_COMPARE2|-|ALT2|SAI5_RX_DATA2|-|ALT5|GPIO5_IO00|-| rowspan="4" |J1.52| rowspan="4" |SAI3_TXD| rowspan="4" |CPU.SAI3_TXD| rowspan="4" |C3| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI3_TX_DATA0|-|ALT1|GPT1_COMPARE3|-|ALT2|SAI5_RX_DATA3|-|ALT5|GPIO5_IO01|-| rowspan="2" |J1.14754| rowspan="2" |GPIO1_IO10| rowspan="2" |CPU.GPIO1_IO10| rowspan="2" |M7| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" |Internally used for ETH PHY interrupt, do not connect|ALT0|GPIO1_IO10|-|ALT1|USB1_OTG_ID|-|J1.56|DGND|DGND|-|<nowiki>-</nowiki>|G
|
|
|
|-
| rowspan="4" |J1.14958| rowspan="4" |SAI5_MCLK| rowspan="4" |CPU.SAI5_MCLK| rowspan="4" |K4| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI5_MCLK|-|ALT1|SAI1_TX_BCLK|-|ALT2|SAI4_MCLK|-|ALT5|GPIO3_IO25
|-
| rowspan="4" |J1.15160|rowspan="4" |GPIO1_IO15| rowspan="4" |CPU.GPIO1_IO15|rowspan="4" |J6|rowspan="4" |NVCC_3V3|rowspan="4" |I/O| rowspan="4" ||ALT0|GPIO1_IO15
|-
|J1.153||||||ALT1|USB2_OTG_OC
|-
|ALT5|PWM4_OUT|-|ALT6|CCM_CLKO2|-| rowspan="3" |J1.15562| rowspan="3" |SAI5_RXFS| rowspan="3" |CPU.SAI5_RXFS| rowspan="3" |N4|rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SAI5_RX_SYNC|-|ALT1|SAI1_TX_DATA0
|-
|J1.157||||||ALT5|GPIO3_IO19
|-
| rowspan="3" |J1.15964|rowspan="3" |SAI5_RXC| rowspan="3" |CPU.SAI5_RXC|rowspan="3" |L5|rowspan="3" |NVCC_3V3|rowspan="3" |I/O| rowspan="3" ||ALT0|SAI5_RX_BCLK
|-
|ALT1|SAI1_TX_DATA1|-|ALT5|GPIO3_IO20|-| rowspan="3" |J1.16166| rowspan="3" |SAI2_TXC| rowspan="3" |CPU.SAI2_TXC| rowspan="3" |J5| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SAI2_TX_BCLK|-|ALT1|SAI5_TX_DATA2|-|ALT5|GPIO4_IO25
|-
| rowspan="3" |J1.16368|rowspan="3" |SAI2_TXD0| rowspan="3" |CPU.SAI2_TXD0|rowspan="3" |G5|rowspan="3" |NVCC_3V3|rowspan="3" |I/O| rowspan="3" ||ALT0|SAI2_TX_DATA0
|-
|J1.165||||||ALT1|SAI5_TX_DATA3
|-
|ALT5|GPIO4_IO26|-| rowspan="3" |J1.70| rowspan="3" |SAI2_TXFS| rowspan="3" |CPU.SAI2_TXFS| rowspan="3" |H4| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SAI2_TX_SYNC|-|ALT1|SAI5_TX_DATA1|-|ALT5|GPIO4_IO24|-| rowspan="3" |J1.16772| rowspan="3" |SAI2_RXD0|rowspan="3" |CPU.SAI2_RXD0|rowspan="3" |H6|rowspan="3" |NVCC_3V3|rowspan="3" |I/O| rowspan="3" ||ALT0|SAI2_RX_DATA0
|-
|J1.169||||||ALT1|SAI5_TX_DATA0
|-
|J1.171||||||ALT5|GPIO4_IO23
|-
| rowspan="3" |J1.74| rowspan="3" |SAI5_RXD0| rowspan="3" |CPU.SAI5_RXD0| rowspan="3" |M5| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SAI5_RX_DATA0 |-|ALT1|SAI1_TX_DATA2|-|ALT5|GPIO3_IO21|-| rowspan="5" |J1.76| rowspan="5" |SAI5_RXD1| rowspan="5" |CPU.SAI5_RXD1| rowspan="5" |L4| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" ||ALT0|SAI5_RX_DATA1|-|ALT1|SAI1_TX_DATA3|-|ALT2|SAI1_TX_SYNC|-|ALT3|SAI5_TX_SYNC|-|ALT5|GPIO3_IO212|-| rowspan="5" |J1.78| rowspan="5" |SAI5_RXD2| rowspan="5" |CPU.SAI5_RXD2| rowspan="5" |M4| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" ||ALT0|SAI5_RX_DATA2|-|ALT1|SAI1_TX_DATA4|-|ALT2|SAI1_TX_SYNC|-|ALT3|SAI5_TX_BCLK|-|ALT5|GPIO3_IO23|-| rowspan="5" |J1.17380| rowspan="5" |SAI5_RXD3| rowspan="5" |CPU.SAI5_RXD3| rowspan="5" |K5| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" ||ALT0|SAI5_RX_DATA3|-|ALT1|SAI1_TX_DATA5|-|ALT2|SAI1_TX_SYNC|-|ALT3|SAI5_TX_DATA0|-|ALT5|GPIO3_IO24|-|J1.82|DGND|DGND| -|<nowiki>-</nowiki>|G
|
|
|
|-
|J1.84
|CLK2_N
|CPU.CLK2_N
|T22
|VDDA_1V8
|D
|Internally used for PCIe CLK, do not connect
|
|
|-
|J1.17586|CLK2_P|CPU.CLK2_P|U22|VDDA_1V8|D|Internally used for PCIe CLK, do not connect
|
|
|-
|J1.88
|PCIE1_REF_CLKN
|CPU.PCIE1_REF_PAD_CLK_N
|K24
|VDD_PHY_3V3
|D
|
|
|
|-
|J1.17790|PCIE1_REF_CLKP|CPU.PCIE1_REF_PAD_CLK_P|K25|VDD_PHY_3V3|D
|
|
|
|-
|J1.92
|PCIE1_RXN
|CPU.PCIE1_RXN_N
|H24
|VDD_PHY_3V3
|D
|
|
|
|-
|J1.17994|PCIE1_RXP|CPU.PCIE1_RXN_P|H25|VDD_PHY_3V3|D
|
|
|
|-
|J1.96
|PCIE1_TXN
|CPU.PCIE1_TXN_N
|J24
|VDD_PHY_3V3
|D
|
|
|
|-
|J1.18198|PCIE1_TXP|CPU.PCIE1_TXN_P|J25|VDD_PHY_3V3|D
|
|
|
|-
|J1.100
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J1.183102|CSI1_CLK_N|CPU.MIPI_CSI1_CLK_N|A22| -|D
|
|
|
|-
|J1.104
|CSI1_CLK_P
|CPU.MIPI_CSI1_CLK_P
|B22
| -
|D
|
|
|
|-
|J1.185106|CSI1_D0_N|CPU.MIPI_CSI1_D0_N|A23| -|D
|
|
|
|-
|J1.108
|CSI1_D0_P
|CPU.MIPI_CSI1_D0_P
|B23
| -
|D
|
|
|
|-
|J1.187110|CSI1_D1_N|CPU.MIPI_CSI1_D1_N|C22| -|D
|
|
|
|-
|J1.112
|CSI1_D1_P
|CPU.MIPI_CSI1_D1_P
|D22
| -
|D
|
|
|
|-
|J1.189114|CSI1_D2_N|CPU.MIPI_CSI1_D2_N|B24| -|D
|
|
|
|-
|J1.116
|CSI1_D2_P
|CPU.MIPI_CSI1_D2_P
|C23
| -
|D
|
|
|
|-
|J1.191118|CSI1_D3_N|CPU.MIPI_CSI1_D3_N|C21| -|D
|
|
|
|-
|J1.120
|CSI1_D3_P
|CPU.MIPI_CSI1_D3_P
|D21
| -
|D
|
|
|
|-
|J1.193122|DGND|DGND| -|<nowiki>-</nowiki>|G
|
|
|
|-
|J1.124
(NAND on board)
|NAND_DQS
|CPU.NAND_DQS
|M20
|NVCC_3V3
|I/O
|Internally used for NAND, do not connect
|
|
|-
| rowspan="3" |J1.124
(eMMC on board)
| rowspan="3" |NAND_DQS
| rowspan="3" |CPU.NAND_DQS
| rowspan="3" |M20
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_DQS
|-
|ALT1
|QSPI_A_DQS
|-
|ALT5
|GPIO3_IO14
|-
|J1.126
(NAND on board)
|NAND_ALE
|CPU.NAND_ALE
|G19
|NVCC_3V3
|I/O
|Internally used for NAND, do not connect
|
|
|-
| rowspan="3" |J1.195126(eMMC on board)| rowspan="3" |NAND_ALE|rowspan="3" |CPU.NAND_ALE|rowspan="3" |G19|rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_ALE
|-
|J1.197||||||ALT1|QSPI_A_SCLK
|-
|J1.199||||||ALT5|GPIO3_IO00
|-
| rowspan="2" |J1.201128(NAND on board)| rowspan="2" |SD1_CLK|rowspan="2" |CPU.SD1_CLK|rowspan="2" |L25|rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_CLK
|-
|ALT5|GPIO2_IO00|-| rowspan="3" |J1.128(eMMC on board)| rowspan="3" |NAND_CE0_B| rowspan="3" |CPU.NAND_CE0_B| rowspan="3" |H19| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_CE0_B|-|ALT1|QSPI_A_SS0_B|-|ALT5|GPIO3_IO01|-| rowspan="2" |J1.130(NAND on board)| rowspan="2" |SD1_CMD| rowspan="2" |CPU.SD1_CMD| rowspan="2" |L24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_CMD|-|ALT5|GPIO2_IO01|-| rowspan="3" |J1.130(eMMC on board)| rowspan="3" |NAND_CE1_B| rowspan="3" |CPU.NAND_CE1_B| rowspan="3" |G21| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_CE1_B|-|ALT1|QSPI_A_SS1_B|-|ALT5|GPIO3_IO02|-| rowspan="2" |J1.132(NAND on board)| rowspan="2" |SD1_RST_B| rowspan="2" |CPU.SD1_RST_B| rowspan="2" |R24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_RESET_B|-|ALT5|GPIO2_IO10|-| rowspan="3" |J1.132(eMMC on board)| rowspan="3" |NAND_CE2_B| rowspan="3" |CPU.NAND_CE2_B| rowspan="3" |F21| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_CE2_B|-|ALT1|QSPI_B_SS0_B|-|ALT5|GPIO3_IO03|-| rowspan="2" |J1.134(NAND on board)| rowspan="2" |SD1_STROBE| rowspan="2" |CPU.SD1_STROBE| rowspan="2" |T24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_STROBE|-|ALT5|GPIO2_IO11|-| rowspan="3" |J1.134(eMMC on board)| rowspan="3" |NAND_CE3_B| rowspan="3" |CPU.NAND_CE3_B| rowspan="3" |H20| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_CE3_B|-|ALT1|QSPI_B_SS1_B|-|ALT5|GPIO3_IO034|-|J1.203136(NAND on board)|NAND_CLE|CPU.NAND_CLE|H21|NVCC_3V3|I/O|Internally used for NAND, do not connect
|
|
|-
|} ===Pinout Table EVEN pins declaration ==rowspan="3" |J1.136(eMMC on board){| classrowspan="wikitable3" |NAND_CLE! latexfontsize| rowspan="scriptsize3" | Pin CPU.NAND_CLE! latexfontsize| rowspan="scriptsize3" | Pin NameH21! latexfontsize| rowspan="scriptsize3" | Internal Connections NVCC_3V3! latexfontsize| rowspan="scriptsize3" | BallI/pin # O! latexfontsize| rowspan="scriptsize3" |<nowiki> Voltage|ALT0|domain</nowiki>RAWNAND_CLE! latexfontsize="scriptsize" | Type -! latexfontsize="scriptsize" | NotesALT1! colspan="2" latexfontsize="scriptsize" | Alternative FunctionsQSPI_B_SCLK
|-
|J1.2||||||ALT5|GPIO3_IO05
|-
| rowspan="2" |J1.4138(NAND on board)| rowspan="2" |SD1_DATA0|rowspan="2" |CPU.SD1_DATA0|rowspan="2" |M25|rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA0
|-
|ALT5|GPIO2_IO02|-| rowspan="3" |J1.6138(eMMC on board)| rowspan="3" |NAND_DATA00| rowspan="3" |CPU.NAND_DATA00| rowspan="3" |G20|rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA00|-|ALT1|QSPI_A_DATA0|-|ALT5|GPIO3_IO06|-| rowspan="2" |J1.140(NAND on board)| rowspan="2" |SD1_DATA1| rowspan="2" |CPU.SD1_DATA1| rowspan="2" |M24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA1|-|ALT5|GPIO2_IO0
|-
| rowspan="3" |J1.8140(eMMC on board)| rowspan="3" |NAND_DATA01|rowspan="3" |CPU.NAND_DATA01|rowspan="3" |J20|rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA01
|-
|J1.10||||||ALT1|QSPI_A_DATA1
|-
|ALT5|GPIO3_IO07|-| rowspan="2" |J1.142(NAND on board)| rowspan="2" |SD1_DATA2| rowspan="2" |CPU.SD1_DATA2| rowspan="2" |N25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA2|-|ALT5|GPIO2_IO04|-| rowspan="3" |J1.142(eMMC on board)| rowspan="3" |NAND_DATA02| rowspan="3" |CPU.NAND_DATA02| rowspan="3" |H22| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA02|-|ALT1|QSPI_A_DATA2|-|ALT5|GPIO3_IO08|-| rowspan="2" |J1.12144(NAND on board)| rowspan="2" |SD1_DATA3| rowspan="2" |CPU.SD1_DATA3| rowspan="2" |P25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA3|-|ALT5|GPIO2_IO05|-| rowspan="3" |J1.144(eMMC on board)| rowspan="3" |NAND_DATA03| rowspan="3" |CPU.NAND_DATA03| rowspan="3" |J21| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA03|-|ALT1|QSPI_A_DATA3|-|ALT5|GPIO3_IO09|-|J1.146|DGND|DGND|-|<nowiki>-</nowiki>|G
|
|
|
|-
| rowspan="2" |J1.148(NAND on board)| rowspan="2" |SD1_DATA4| rowspan="2" |CPU.SD1_DATA4| rowspan="2" |N24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA4|-|ALT5|GPIO2_IO06|-| rowspan="3" |J1.148(eMMC on board)| rowspan="3" |NAND_DATA04| rowspan="3" |CPU.NAND_DATA04| rowspan="3" |L20| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA04|-|ALT1|QSPI_B_DATA0|-|ALT5|GPIO3_IO10|-| rowspan="2" |J1.150(NAND on board)| rowspan="2" |SD1_DATA5| rowspan="2" |CPU.SD1_DATA5| rowspan="2" |P24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA5|-|ALT5|GPIO2_IO07|-| rowspan="3" |J1.150(eMMC on board)| rowspan="3" |NAND_DATA05| rowspan="3" |CPU.NAND_DATA05| rowspan="3" |J22| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA05|-|ALT1|QSPI_B_DATA1|-|ALT5|GPIO3_IO11|-| rowspan="2" |J1.152(NAND on board)| rowspan="2" |SD1_DATA6| rowspan="2" |CPU.SD1_DATA6| rowspan="2" |R25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA6|-|ALT5|GPIO2_IO08|-| rowspan="3" |J1.152(eMMC on board)| rowspan="3" |NAND_DATA06| rowspan="3" |CPU.NAND_DATA06| rowspan="3" |L19| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA06|-|ALT1|QSPI_B_DATA2|-|ALT5|GPIO3_IO12|-| rowspan="2" |J1.154(NAND on board)| rowspan="2" |SD1_DATA7| rowspan="2" |CPU.SD1_DATA7| rowspan="2" |T25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA7|-|ALT5|GPIO2_IO09|-| rowspan="3" |J1.14154(eMMC on board)| rowspan="3" |NAND_DATA07| rowspan="3" |CPU.NAND_DATA07| rowspan="3" |M19| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA07|-|ALT1|QSPI_B_DATA3|-|ALT5|GPIO3_IO13|-|J1.156(NAND on board)|NAND_RE_B|CPU.NAND_RE_B|K19|NVCC_3V3|I/O|Internally used for NAND, do not connect
|
|
|-
| rowspan="3" |J1.156
(eMMC on board)
| rowspan="3" |NAND_RE_B
| rowspan="3" |CPU.NAND_RE_B
| rowspan="3" |K19
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_RE_B
|-
|ALT1
|QSPI_B_DQS
|-
|ALT5
|GPIO3_IO15
|-
|J1.158
(NAND on board)
|NAND_READY_B
|CPU.NAND_READY_B
|K20
|NVCC_3V3
|I/O
|Internally used for NAND, do not connect
|
|
|-
| rowspan="2" |J1.16158(eMMC on board)| rowspan="2" |NAND_READY_B| rowspan="2" |CPU.NAND_READY_B| rowspan="2" |K20| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|RAWNAND_READY_B|-|ALT5|GPIO3_IO16|-|J1.160(NAND on board)|NAND_WE_B|CPU.NAND_WE_B|K22|NVCC_3V3|I/O|Internally used for NAND, do not connect
|
|
|-
| rowspan="2" |J1.160
(eMMC on board)
| rowspan="2" |NAND_WE_B
| rowspan="2" |CPU.NAND_WE_B
| rowspan="2" |K22
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|RAWNAND_WE_B
|-
|ALT5
|GPIO3_IO17
|-
|J1.162
(NAND on board)
|NAND_WP_B
|CPU.NAND_WP_B
|K21
|NVCC_3V3
|I/O
|Internally used for NAND, do not connect
|
|
|-
| rowspan="2" |J1.162
(eMMC on board)
| rowspan="2" |NAND_WP_B
| rowspan="2" |CPU.NAND_WP_B
| rowspan="2" |K21
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|RAWNAND_WP_B
|-
|ALT5
|GPIO3_IO18
|-
|J1.164
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J1.18166|CLK1_N|CPU.CLK1_N|T23||D
|
|
|
|-
|J1.168
|CLK1_P
|CPU.CLK1_P
|R23
|
|D
|
|
|
|-
|J1.20170|USB2_RXN|CPU.USB2_RX_N|B8
|
|D
|
|
|
|-
|J1.172
|USB2_RXP
|CPU.USB2_RX_P
|A8
|
|D
|
|
|
|-
|J1.22174|USB2_TXN|CPU.USB2_TX_N|B9||D
|
|
|
|-
|J1.176
|USB2_TXP
|CPU.USB2_TX_P
|A9
|
|D
|
|
|
|-
|J1.24178|USB1_RXN|CPU.USB1_RX_N|B12||D
|
|
|
|-
|J1.180
|USB1_RXP
|CPU.USB1_RX_P
|A12
|
|D
|
|
|
|-
|J1.26182|USB1_TXN|CPU.USB1_TX_N|B13
|
|D
|
|
|
|-
|J1.28184|USB1_TXP|CPU.USB1_TX_P|A13
|
|D
|
|
|
|-
|J1.186
|USB1_VBUS
|CPU.USB1_VBUS
|D14
| -
|S
|Absolute maximum ratings 5.25V
|
|
|-
|J1.188
|USB2_VBUS
|CPU.USB2_VBUS
|D9
| -
|S
|Absolute maximum ratings 5.25V
|
|
|-
|J1.30190|DGND|DGND| -|<nowiki>-</nowiki>|G
|
|
|
|-
|J1.192
|USB1_ID
|CPU.USB1_ID
|C14
|VDD_PHY_3V3
|I
|
|
|
|-
|J1.32194|USB2_ID|CPU.USB2_ID|C9|VDD_PHY_3V3|I
|
|
|
|-
|J1.196
|USB1_DN
|CPU.USB1_DN
|B14
| -
|D
|
|
|
|-
|J1.34198|USB1_DP|CPU.USB1_DP|A14| -|D
|
|
|
|-
|J1.200
|USB2_DP
|CPU.USB2_DP
|A10
| -
|D
|
|
|
|-
|J1.36202|USB2_DN|CPU.USB2_DN|B10| -|D
|
|
|
|-
|J1.204
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J1} ==ONE PIECE J4 pins declaration =={| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" | Voltage domain! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! colspan="2" |Alternative Functions|-|J4.381|DGND|DGND|-|<nowiki>-</nowiki>|G
|
|
|
|-
|J1rowspan="7" |J4.2| rowspan="7" |SAI1_RXD7| rowspan="7" |CPU.SAI1_RXD7| rowspan="7" |G1| rowspan="7" |NVCC_3V3| rowspan="7" |I/O| rowspan="7" |Internally used for BOOT configCould be pulled-up or down during bootstrap.40|ALT0|SAI1_RX_DATA7|-|ALT1|SAI6_MCLK|-|ALT2|SAI1_TX_SYNC|-|ALT3|SAI1_TX_DATA4
|-
|J1.42||||||ALT4|CORESIGHT_TRACE7
|-
|J1.44||||||ALT5|GPIO4_IO09
|-
|J1ALT6|SRC_BOOT_CFG7|-| rowspan="6" |J4.463| rowspan="6" |SAI1_RXD6|rowspan="6" |CPU.SAI1_RXD6|rowspan="6" |G2|rowspan="6" |NVCC_3V3|rowspan="6" |I/O|rowspan="6" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_RX_DATA6
|-
|J1.48||||||ALT1|SAI6_TX_SYNC
|-
|J1.50||||||ALT2|SAI6_RX_SYNC
|-
|J1.52||||||ALT4|CORESIGHT_TRACE6
|-
|J1ALT5|GPIO4_IO08|-|ALT6|SRC_BOOT_CFG6|-| rowspan="7" |J4.4| rowspan="7" |SAI1_RXD5| rowspan="7" |CPU.54SAI1_RXD5|rowspan="7" |F1|rowspan="7" |NVCC_3V3| rowspan="7" |I/O| rowspan="7" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_RX_DATA5|-|ALT1|SAI6_TX_DATA0
|-
|J1.56||||||ALT2|SAI6_RX_DATA0
|-
|J1.58||||||ALT3|SAI1_RX_SYNC
|-
|J1.60ALT4|CORESIGHT_TRACE5|-|ALT5|GPIO4_IO07|-|ALT6|SRC_BOOT_CFG5
|-
|J1rowspan="6" |J4.625|rowspan="6" |SAI1_RXD4| rowspan="6" |CPU.SAI1_RXD4|rowspan="6" |J1|rowspan="6" |NVCC_3V3|rowspan="6" |I/O|rowspan="6" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_RX_DATA4
|-
|J1.64||||||ALT1|SAI6_TX_BCLK
|-
|J1.66||||||ALT2|SAI6_RX_BCLK
|-
|J1.68|||ALT4|CORESIGHT_TRACE4|-|ALT5|GPIO4_IO06
|-
|J1.70||||||ALT6|SRC_BOOT_CFG4
|-
|J1rowspan="5" |J4.726| rowspan="5" |SAI1_RXD3|rowspan="5" |CPU.SAI1_RXD3|rowspan="5" |J2|rowspan="5" |NVCC_3V3|rowspan="5" |I/O|rowspan="5" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_RX_DATA3
|-
|J1.74||||||ALT1|SAI5_RX_DATA3
|-
|J1ALT4|CORESIGHT_TRACE3|-|ALT5|GPIO4_IO05|-|ALT6|SRC_BOOT_CFG3|-| rowspan="5" |J4.767| rowspan="5" |SAI1_RXD2| rowspan="5" |CPU.SAI1_RXD2| rowspan="5" |H2|rowspan="5" |NVCC_3V3|rowspan="5" |I/O| rowspan="5" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_RX_DATA2|-|ALT1|SAI5_RX_DATA2
|-
|J1.78||||||ALT4|CORESIGHT_TRACE2
|-
|J1.80||||||ALT5|GPIO4_IO04
|-
|J1ALT6|SRC_BOOT_CFG2|-| rowspan="5" |J4.8| rowspan="5" |SAI1_RXD1| rowspan="5" |CPU.SAI1_RXD1| rowspan="5" |L2| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_RX_DATA1|-|ALT1|SAI5_RX_DATA1|-|ALT4|CORESIGHT_TRACE1|-|ALT5|GPIO4_IO03|-|ALT6|SRC_BOOT_CFG1|-| rowspan="5" |J4.9| rowspan="5" |SAI1_RXD0| rowspan="5" |CPU.SAI1_RXD0| rowspan="5" |K2| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_RX_DATA0|-|ALT1|SAI5_RX_DATA0|-|ALT4|CORESIGHT_TRACE0|-|ALT5|GPIO4_IO02|-|ALT6|SRC_BOOT_CFG0|-| rowspan="4" |J4.10| rowspan="4" |SAI1_RXC| rowspan="4" |CPU.SAI1_RXC| rowspan="4" |K1| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI1_RX_BCLK|-|ALT1|SAI5_RX_BCLK|-|ALT4|CORESIGHT_TRACE_CTL|-|ALT5|GPIO4_IO01|-| rowspan="4" |J4.11| rowspan="4" |SAI1_RXFS| rowspan="4" |CPU.82SAI1_RXFS| rowspan="4" |L1| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI1_RX_SYNC|-|ALT1|SAI5_RX_SYNC|-|ALT4|CORESIGHT_TRACE_CLK|-|ALT5|GPIO4_IO00|-|J4.12|DGND|DGND|-|<nowiki>-</nowiki>|G
|
|
|
|-
|J1rowspan="4" |J4.13| rowspan="4" |SAI1_MCLK| rowspan="4" |CPU.84SAI1_MCLK| rowspan="4" || rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI1_MCLK|-|ALT1|SAI5_MCLK |-|ALT2|SAI1_TX_BCLK|-|ALT5|GPIO4_IO20
|-
|J1J4.8614|DGND|DGND|-|<nowiki>-</nowiki>|G
|
|
|
|-
|J1rowspan="4" |J4.8815|rowspan="4" |SAI1_TXFS| rowspan="4" |CPU.SAI1_TXFS|rowspan="4" |H4|rowspan="4" |NVCC_3V3|rowspan="4" |I/O| rowspan="4" ||ALT0|SAI1_TX_SYNC
|-
|J1ALT1|SAI5_TX_SYNC|-|ALT4|CORESIGHT_EVENTO|-|ALT5|GPIO4_IO10|-| rowspan="4" |J4.9016| rowspan="4" |SAI1_TXC|rowspan="4" |CPU.SAI1_TXC|rowspan="4" |J5|rowspan="4" |NVCC_3V3|rowspan="4" |I/O| rowspan="4" ||ALT0|SAI1_TX_BCLK
|-
|J1.92||||||ALT1|SAI5_TX_BCLK
|-
|J1.94||||||ALT4|CORESIGHT_EVENTI
|-
|J1ALT5|GPIO4_IO11|-| rowspan="5" |J4.17| rowspan="5" |SAI1_TXD0| rowspan="5" |CPU.SAI1_TXD0| rowspan="5" |F2| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" |Internally used for BOOT configCould be pulled-up or down during bootstrap.96|ALT0|SAI1_TX_DATA0|-|ALT1|SAI5_TX_DATA0|-|ALT4|CORESIGHT_TRACE8
|-
|J1.98||||||ALT5|GPIO4_IO12
|-
|J1.100||||||ALT6|SRC_BOOT_CFG8
|-
|J1rowspan="5" |J4.18| rowspan="5" |SAI1_TXD1| rowspan="5" |CPU.SAI1_TXD1| rowspan="5" |E2| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" |Internally used for BOOT configCould be pulled-up or down during bootstrap.102|ALT0|SAI1_TX_DATA1|-|ALT1|SAI5_TX_DATA1|-|ALT4|CORESIGHT_TRACE9|-|ALT5|GPIO4_IO13|-|ALT6|SRC_BOOT_CFG9
|-
|J1rowspan="5" |J4.10419| rowspan="5" |SAI1_TXD2|rowspan="5" |CPU.SAI1_TXD2|rowspan="5" |B2|rowspan="5" |NVCC_3V3|rowspan="5" |I/O|rowspan="5" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_TX_DATA2
|-
|J1.106||||||ALT1|SAI5_TX_DATA2
|-
|J1ALT4|CORESIGHT_TRACE10|-|ALT5|GPIO4_IO14|-|ALT6|SRC_BOOT_CFG10|-| rowspan="5" |J4.10820| rowspan="5" |SAI1_TXD3| rowspan="5" |CPU.SAI1_TXD3| rowspan="5" |D1|rowspan="5" |NVCC_3V3|rowspan="5" |I/O| rowspan="5" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_TX_DATA3|-|ALT1|SAI5_TX_DATA3
|-
|J1.110||||||ALT4|CORESIGHT_TRACE11
|-
|J1.112||||||ALT5|GPIO4_IO15
|-
|J1ALT6|SRC_BOOT_CFG11|-| rowspan="6" |J4.21| rowspan="6" |SAI1_TXD4| rowspan="6" |CPU.SAI1_TXD4| rowspan="6" |D2| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT configCould be pulled-up or down during bootstrap.114|ALT0|SAI1_TX_DATA4|-|ALT1|SAI6_RX_BCLK|-|ALT2|SAI6_TX_BCLK|-|ALT4|CORESIGHT_TRACE12
|-
|J1.116||||||ALT5|GPIO4_IO16
|-
|J1.118||||||ALT6|SRC_BOOT_CFG12
|-
|J1rowspan="6" |J4.22| rowspan="6" |SAI1_TXD5| rowspan="6" |CPU.SAI1_TXD5| rowspan="6" |C2| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_TX_DATA5|-|ALT1|SAI6_RX_DATA0|-|ALT2|SAI6_TX_DATA0|-|ALT4|CORESIGHT_TRACE13|-|ALT5|GPIO4_IO17|-|ALT6|SRC_BOOT_CFG13|-| rowspan="6" |J4.23| rowspan="6" |SAI1_TXD6| rowspan="6" |CPU.SAI1_TXD6| rowspan="6" |B3| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT configCould be pulled-up or down during bootstrap.120|ALT0|SAI1_TX_DATA6|-|ALT1|SAI6_RX_SYNC|-|ALT2|SAI6_TX_SYNC|-|ALT4|CORESIGHT_TRACE14|-|ALT5|GPIO4_IO18|-|ALT6|SRC_BOOT_CFG14|-| rowspan="5" |J4.24| rowspan="5" |SAI1_TXD7| rowspan="5" |CPU.SAI1_TXD7| rowspan="5" |C1| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_TX_DATA7|-|ALT1|SAI6_MCLK|-|ALT4|CORESIGHT_TRACE15|-|ALT5|GPIO4_IO19|-|ALT6|SRC_BOOT_CFG15
|-
|J1J4.12225|DGND|DGND| -|<nowiki>-</nowiki>|G
|
|
|
|}
 
==ONE PIECE J5 pins declaration ==
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" | Voltage domain
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
! colspan="2" |Alternative Functions
|-
|J5.1
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J1J5.1242|PCIE2_RXN|CPU.PCIE2_RXN_N|D24| -|D
|
|
|
|-
|J5.3
|PCIE2_RXP
|CPU.PCIE2_RXN_P
|D25
| -
|D
|
|
|
|-
|J1J5.1264|DGND|DGND| -|<nowiki>-</nowiki>|G
|
|
|
|-
|J5.5
|PCIE2_TXN
|CPU.PCIE2_TXN_N
|E24
| -
|D
|
|
|
|-
|J1J5.1286|PCIE2_TXP|CPU.PCIE2_TXN_P|E25| -|D
|
|
|
|-
|J5.7
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J1J5.1308|PCIE2_REF_CLKN|CPU.PCIE2_REF_PAD_CLK_N|F24| -|D
|
|
|
|-
|J5.9
|PCIE2_REF_CLKP
|CPU.PCIE2_REF_PAD_CLK_P
|F25
| -
|D
|
|
|
|-
|J1J5.13210|DGND|DGND| -|<nowiki>-</nowiki>|G
|
|
|
|-
|J5.11
|CSI_P2_CKN
|CPU.MIPI_CSI2_CLK_N
|A19
| -
|D
|
|
|
|-
|J1J5.13412|CSI_P2_CKP|CPU.MIPI_CSI2_CLK_P|B19| -|D
|
|
|
|-
|J5.13
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J1J5.13614|CSI_P2_DN0|CPU.MIPI_CSI2_D0_N|C20| -|D
|
|
|
|-
|J5.15
|CSI_P2_DP0
|CPU.MIPI_CSI2_D0_P
|D10
| -
|D
|
|
|
|-
|J1J5.13816|CSI_P2_DN1|CPU.MIPI_CSI2_D1_N|A20| -|D
|
|
|
|-
|J5.17
|CSI_P2_DP1
|CPU.MIPI_CSI2_D1_P
|B20
| -
|D
|
|
|
|-
|J1J5.14018|DGND|DGND| -|<nowiki>-</nowiki>|G
|
|
|
|-
|J5.19
|CSI_P2_DN2
|CPU.MIPI_CSI2_D2_N
|A21
| -
|D
|
|
|
|-
|J1J5.14220|CSI_P2_DP2|CPU.MIPI_CSI2_D2_P|B21| -|D
|
|
|
|-
|J5.21
|CSI_P2_DN3
|CPU.MIPI_CSI2_D3_N
|C19
| -
|D
|
|
|
|-
|J1J5.14422|CSI_P2_DP3|CPU.MIPI_CSI2_D3_P|D19| -|D
|
|
|
|-
|J5.23
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J1rowspan="4" |J5.14624|rowspan="4" |I2C4_SCL| rowspan="4" |CPU.I2C4_SCL|rowspan="4" |F8|rowspan="4" |NVCC_3V3|rowspan="4" |I/O| rowspan="4" ||ALT0|I2C4_SCL
|-
|J1.148|||ALT1|PWM2_OUT|-|ALT2|PCIE1_CLKREQ_B
|-
|J1.150||||||ALT5|GPIO5_IO20
|-
|J1rowspan="4" |J5.15225|rowspan="4" |I2C4_SDA| rowspan="4" |CPU.I2C4_SDA|rowspan="4" |F9|rowspan="4" |NVCC_3V3|rowspan="4" |I/O| rowspan="4" ||ALT0|I2C4_SDA
|-
|J1.154||||||ALT1|PWM1_OUT
|-
|J1.156||||||||-|J1.158||||||||-|J1.160||||||||-|J1.162||||||||-|J1.164||||||||-|J1.166||||||||-|J1.168||||||||-|J1.170||||||||-|J1.172||||||||-|J1.174||||||||-|J1.176||||||||-|J1.178||||||||-|J1.180||||||||-|J1.182||||||||-|J1.184||||||||-|J1.186||||||||-|J1.188||||||||-|J1.190||||||||-|J1.192||||||||-|J1.194||||||||-|J1.196||||||||-|J1.198||||||||-|J1.200||||||||-|J1.202||||||||-|J1.204||||||ALT2|PCIE2_CLKREQ_B
|-
|ALT5
|GPIO5_IO21
|}
U0007
Bureaucrats, dave_user, Administrators
8,286
edits
Retrieved from "https://wiki.dave.eu/index.php/Special:MobileDiff/10198...19065"