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MITO 8M SOM/MITO 8M Hardware/Pinout Table

4,036 bytes added, 17:49, 28 December 2023
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<section begin="History" />
{| style="border-collapse:collapse; "
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
|-
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0{{oldid| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" 10368|Sep 2020/09/29}}
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |2021/02/02
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |Add pull-up/down information
|-
|}
<section end="History" /><section begin="Body" />==Connectors and Pinout Table=====Introduction=description==
This chapter contains the pinout === Connectors description of ===In the following table are described all available connectors integrated on MITO 8M module, grouped in two tables (odd and even pins) that report the SOM:{| class="wikitable"|-!Connector name!Connector Type!Notes!Carrier board counterpart|-|J1|SODIMM edge connector 204 pin mapping of the 204|partially compatible with [[AXEL Lite SOM]]|TE Connectivity 2-2013289-1|-|J4|ONE PIECE connector single row 25pins||SAMTEC FSI-125-03-G-S-AD-TR|-|J5|ONE PIECE connector single row 25pins||SAMTEC FSI-125-03-G-S-pin SOAD-DIMM TR|}The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to MITO 8M connectorpinout specifications.See the images below for reference:
[[File:MITO 8M-conn-TOP.png|500px|thumb|MITO 8M TOP view|none]]
[[File:MITO 8M-conn-BOTTOM.png|500px|thumb|MITO 8M BOTTOM view|none]]
 
Below a detailed description of the pinout, grouped in the following tables:
* two tables (ODD and EVEN pins) that report the pin mapping of the 204-pin SO-DIMM edge
* a dedicated tables for J4 one-piece connector
* a dedicated tables for J5 one-piece connector
 
=== Pinout Table description ===
Each row in the pinout tables contains the following information:
 {| class="wikitable" style="width:50%;"
|-
|'''Pin'''
|-
|'''Pin Name'''
| Pin (signal) name on the AxelLite MITO 8M connectors
|-
|'''Internal<br>connections'''
| Connections to the Axel Ultra components
* CPU.<x> : pin connected to CPU pad named <x>
* PMIC.<x> : pin connected to the Power Manager IC(NXP PF4210)* LAN.<x> : pin connected to the LAN PHY(MICROCHIP KSZ9031RNX)* BRIDGE.<x> : pin connected to the MIPI-to-LVDS bridge* SV.<x>: pin connected to voltage supervisor(TI SN65DSI84)
|-
|'''Ball/pin #'''
|}
===Pinout Table SODIMM J1 ODD pins declaration ===
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| colspan="2" |
|-
|J1.3
|S
|
| colspan="2" |
|-
|J1.5
|S
|
| colspan="2" |
|-
|J1.7
|S
|
| colspan="2" |
|-
|J1.9
|S
|
| colspan="2" |
|-
|J1.11
|G
|
| colspan="2" |
|-
|J1.13
|NVCC_1V8
|I/O
|must Must be level translated if used @ 3V3Internally pulled-up to 1.8V during bootstrap| colspan="2" |
|-
|J1.15
|NVCC_1V8
|I/O
|must Must be level translated if used @ 3V3Internally pulled-up to 1.8V during bootstrap| colspan="2" |
|-
|J1.17
|G
|
| colspan="2" |
|-
|J1.19
|D
|
| colspan="2" |
|-
|J1.21
|D
|
| colspan="2" |
|-
|J1.23
|D
|
| colspan="2" |
|-
|J1.25
|D
|
| colspan="2" |
|-
|J1.27
|D
|
| colspan="2" |
|-
|J1.29
|D
|
| colspan="2" |
|-
|J1.31
|D
|
| colspan="2" |
|-
|J1.33
|D
|
| colspan="2" |
|-
|J1.35
|G
|
| colspan="2" |
|-
| rowspan="4" |J1.37
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for ETH PHY reset, do not connect
|ALT0
|GPIO1_IO01
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |Internally used, do not connect
|ALT0
|GPIO1_IO13
|
|
| colspan="2" |
|-
| rowspan="3" |J1.47
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| colspan="2" |
|-
| rowspan="3" |J1.59
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |Internally used for MIPI-to-LVDS interrupt, do not connectPulled-up to NVCC_3V3
|ALT0
|GPIO1_IO05
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for MIPI-to-LVDS enable, do not connect
|ALT0
|GPIO1_IO06
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| colspan="2" |
|-
| rowspan="2" |J1.75
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| colspan="2" |
|-
| rowspan="3" |J1.89
|I/O
|
| colspan="2" |
|-
|J1.103
|I/O
|
| colspan="2" |
|-
|J1.105
|D
|connected with capacitor in series
| colspan="2" |
|-
|J1.107
|D
|connected with capacitor in series
| colspan="2" |
|-
|J1.109
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| colspan="2" |
|-
|J1.111
|D
|connected with capacitor in series
| colspan="2" |
|-
|J1.113
|D
|connected with capacitor in series
| colspan="2" |
|-
|J1.115
|D
|connected with capacitor in series
| colspan="2" |
|-
|J1.117
|D
|connected with capacitor in series
| colspan="2" |
|-
|J1.119
|D
|connected with capacitor in series
| colspan="2" |
|-
|J1.121
|D
|connected with capacitor in series
| colspan="2" |
|-
|J1.123
|D
|connected with capacitor in series
| colspan="2" |
|-
|J1.125
|D
|connected with capacitor in series
| colspan="2" |
|-
|J1.127
|I/O
|
| colspan="2" |
|-
|J1.129
|I/O
|
| colspan="2" |
|-
|J1.131
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| colspan="2" |
|-
|J1.133
|D
|
| colspan="2" |
|-
|J1.135
|D
|
| colspan="2" |
|-
|J1.137
|D
|
| colspan="2" |
|-
|J1.139
|D
|
| colspan="2" |
|-
|J1.141
|D
|
| colspan="2" |
|-
|J1.143
|D
|
| colspan="2" |
|-
|J1.145
|D
|
| colspan="2" |
|-
|J1.147
|D
|
| colspan="2" |
|-
|J1.149
|D
|
| colspan="2" |
|-
|J1.151
|D
|
| colspan="2" |
|-
|J1.153
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| colspan="2" |
|-
|J1.155
|D
|
| colspan="2" |
|-
|J1.157
|D
|
| colspan="2" |
|-
|J1.159
|D
|
| colspan="2" |
|-
|J1.161
|D
|
| colspan="2" |
|-
|J1.163
|D
|
| colspan="2" |
|-
|J1.165
|D
|
| colspan="2" |
|-
|J1.167
|D
|
| colspan="2" |
|-
|J1.169
|D
|
| colspan="2" |
|-
|J1.171
|D
|
| colspan="2" |
|-
|J1.173
|D
|
| colspan="2" |
|-
|J1.175
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| colspan="2" |
|-
| rowspan="2" |J1.177
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="63" |used as default Linux console
|ALT0
|UART2_TX
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |used as default Linux console
|ALT0
|UART2_RXD
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| colspan="2" |
|-
|}
===Pinout Table SODIMM J1 EVEN pins declaration ===
{| class="wikitable"
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
|G
|
| colspan="2" |
|-
|J1.4
|S
|
| colspan="2" |
|-
|J1.6
|S
|
| colspan="2" |
|-
|J1.8
|S
|
| colspan="2" |
|-
|J1.10
|S
|
| colspan="2" |
|-
|J1.12
|G
|
| colspan="2" |
|-
|J1.14
|S
|
| colspan="2" |
|-
|J1.16
|I
|internal pull-up 100k to NVCC_SNVS
| colspan="2" |
|-
|J1.18
|O
|
| colspan="2" |
|-
|J1.20
|I
|internal pull-up to NVCC_3V3
| colspan="2" |
|-
|J1.22
|I/O
|internal pull-up 100k to NVCC_SNVS
| colspan="2" |
|-
|J1.24
|I
|internal pull-up to NVCC_SNVS
| colspan="2" |
|-
| rowspan="4" |J1.26
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for SW reset, do not connect
|ALT0
|GPIO1_IO02
|G
|
| colspan="2" |
|-
| rowspan="4" |J1.32
|-
| rowspan="2" |J1.54
| rowspan="2" |SD1_STROBEGPIO1_IO10| rowspan="2" |CPU.SD1_STROBEGPIO1_IO10| rowspan="2" |T24M7| rowspan="2" |NVCC_3V3 when available(NVCC_1V8 on request)
| rowspan="2" |I/O
| rowspan="2" |Internally used for eMMCETH PHY interrupt, do not connect(available on NAND storage SOM version)
|ALT0
|USDHC1_STROBE GPIO1_IO10
|-
|ALT5ALT1|GPIO2_IO11USB1_OTG_ID
|-
|J1.56
|G
|
| colspan="2" |
|-
| rowspan="4" |J1.58
|G
|
| colspan="2" |
|-
|J1.84
|VDDA_1V8
|D
|Internally used for PCIe CLK, do not connect
|
|
| colspan="2" |
|-
|J1.86
|VDDA_1V8
|D
|Internally used for PCIe CLK, do not connect
|
|
| colspan="2" |
|-
|J1.88
|D
|
| colspan="2" |
|-
|J1.90
|D
|
| colspan="2" |
|-
|J1.92
|D
|
| colspan="2" |
|-
|J1.94
|D
|
| colspan="2" |
|-
|J1.96
|D
|
| colspan="2" |
|-
|J1.98
|D
|
| colspan="2" |
|-
|J1.100
|G
|
| colspan="2" |
|-
|J1.102
|D
|
| colspan="2" |
|-
|J1.104
|D
|
| colspan="2" |
|-
|J1.106
|D
|
| colspan="2" |
|-
|J1.108
|D
|
| colspan="2" |
|-
|J1.110
|D
|
| colspan="2" |
|-
|J1.112
|D
|
| colspan="2" |
|-
|J1.114
|D
|
| colspan="2" |
|-
|J1.116
|D
|
| colspan="2" |
|-
|J1.118
|D
|
| colspan="2" |
|-
|J1.120
|D
|
| colspan="2" |
|-
|J1.122
|G
|
| colspan="2" ||-|J1.124(NAND on board)|NAND_DQS|CPU.NAND_DQS|M20|NVCC_3V3|I/O|Internally used for NAND, do not connect||
|-
| rowspan="3" |J1.124
(eMMC on board)
| rowspan="3" |NAND_DQS
| rowspan="3" |CPU.NAND_DQS
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |Internally used for NAND, do not connect(available on eMMC storage SOM version)
|ALT0
|RAWNAND_DQS
|ALT5
|GPIO3_IO14
|-
|J1.126
(NAND on board)
|NAND_ALE
|CPU.NAND_ALE
|G19
|NVCC_3V3
|I/O
|Internally used for NAND, do not connect
|
|
|-
| rowspan="3" |J1.126
(eMMC on board)
| rowspan="3" |NAND_ALE
| rowspan="3" |CPU.NAND_ALE
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |Internally used for NAND, do not connect(available on eMMC storage SOM version)
|ALT0
|RAWNAND_ALE
|-
|ALT1
|QSPI_A_SCLK
|-
|ALT5
|GPIO3_IO00
|-
| rowspan="52" |J1.128(NAND on board)| rowspan="2" |SD1_CLK| rowspan="52" |NAND_CE0_B CPU.SD1_CLK| rowspan="2" |L25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I// SD1_CLKO| rowspan="2" ||ALT0|USDHC1_CLK|-|ALT5|GPIO2_IO00|-| rowspan="3" |CPUJ1.NAND_CE0_B 128(eMMC storage SOM versionon board)| rowspan="3" |NAND_CE0_B| rowspan="3" |CPU.NAND_CE0_B
| rowspan="3" |H19
| rowspan="53" |NVCC_3V3 (NVCC_1V8 on request)| rowspan="53" |I/O| rowspan="53" |
|ALT0
|RAWNAND_CE0_B
|GPIO3_IO01
|-
| rowspan="2" |J1.130(NAND on board)| rowspan="2" |SD1_CMD| rowspan="2" |CPU.SD1_CLK SD1_CMD| rowspan="2" |L24| rowspan="2" |NVCC_3V3(NAND storage SOM versionNVCC_1V8 on request)| rowspan="2" |L25I/O| rowspan="2" |
|ALT0
|USDHC1_CLKUSDHC1_CMD
|-
|ALT5
|GPIO2_IO00GPIO2_IO01
|-
| rowspan="3" |J1.130(eMMC on board)| rowspan="3" |NAND_CE1_B // SD1_CMD| rowspan="3" |CPU.NAND_CE1_B // CPU.SD1_CMD| rowspan="3" |G21 // L24|NVCC_1V8 // rowspan="3" |NVCC_3V3 ???| rowspan="3" |I/O|???rowspan="3" ||ALT0|RAWNAND_CE1_B
|-
|J1.132|NAND_CE2_B // SD1_RST_B|CPU.NAND_CE2_B // CPU.SD1_RST_B|F21 // R24|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT1|QSPI_A_SS1_B
|-
|J1.134|NAND_CE3_B // SD1_STROBE|CPU.NAND_CE3_B // CPU.SD1_STROBE|H20 // T24|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT5|GPIO3_IO02
|-
| rowspan="2" |J1.136132(NAND on board)|NAND_CLErowspan="2" |SD1_RST_B|DGNDrowspan="2" |CPU.SD1_RST_B|H21rowspan="2" |R24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_RESET_B
|-
|J1.138|NAND_DATA00 // SD1_DATA0|CPU.NAND_DATA00 // CPU.SD1_DATA0|G20 // M25|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT5|GPIO2_IO10
|-
| rowspan="3" |J1.140132(eMMC on board)|NAND_DATA01 // SD1_DATA1rowspan="3" |NAND_CE2_B| rowspan="3" |CPU.NAND_DATA01 /NAND_CE2_B| rowspan="3" |F21| rowspan="3" |NVCC_3V3| rowspan="3" |I/ O| rowspan="3" ||ALT0|RAWNAND_CE2_B|-|ALT1|QSPI_B_SS0_B|-|ALT5|GPIO3_IO03|-| rowspan="2" |J1.134(NAND on board)| rowspan="2" |SD1_STROBE| rowspan="2" |CPU.SD1_DATA1SD1_STROBE|J20 // M24rowspan="2" |T24|rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I// O| rowspan="2" ||ALT0|USDHC1_STROBE|-|ALT5|GPIO2_IO11|-| rowspan="3" |J1.134(eMMC on board)| rowspan="3" |NAND_CE3_B| rowspan="3" |CPU.NAND_CE3_B| rowspan="3" |H20| rowspan="3" |NVCC_3V3 ???| rowspan="3" |I/O|???rowspan="3" ||ALT0|RAWNAND_CE3_B|-|ALT1|QSPI_B_SS1_B
|-
|J1.142|NAND_DATA02 // SD1_DATA2|CPU.NAND_DATA02 // CPU.SD1_DATA2|H22 // N25|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT5|GPIO3_IO034
|-
|J1.144136(NAND on board)|NAND_DATA03 // SD1_DATA3NAND_CLE|CPU.NAND_DATA03 // CPU.SD1_DATA3NAND_CLE|J21 // P25H21|NVCC_1V8 // NVCC_3V3 ???
|I/O
|???Internally used for NAND, do not connect
|
|
|-
| rowspan="3" |J1.146136(eMMC on board)| rowspan="3" |DGNDNAND_CLE|DGNDrowspan="3" |CPU.NAND_CLE| -rowspan="3" |H21|<nowiki>-<rowspan="3" |NVCC_3V3| rowspan="3" |I/nowiki>O|Growspan="3" ||ALT0|RAWNAND_CLE
|-
|J1.148|NAND_DATA04 // SD1_DATA4|CPU.NAND_DATA04 // CPU.SD1_DATA4|L20 // N24|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT1|QSPI_B_SCLK
|-
|J1.150|NAND_DATA05 // SD1_DATA5|CPU.NAND_DATA05 // CPU.SD1_DATA5|J22 // P24|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT5|GPIO3_IO05
|-
| rowspan="2" |J1.152138(NAND on board)| rowspan="2" |NAND_DATA06 // SD1_DATA6SD1_DATA0| rowspan="2" |CPU.NAND_DATA06 // CPU.SD1_DATA6SD1_DATA0|L19 // R25rowspan="2" |M25|rowspan="2" |NVCC_3V3(NVCC_1V8 // NVCC_3V3 ???on request)| rowspan="2" |I/O|???rowspan="2" ||ALT0|USDHC1_DATA0
|-
|J1.154|NAND_DATA07 // SD1_DATA7|CPU.NAND_DATA07 // CPU.SD1_DATA7|M19 // T25|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT5|GPIO2_IO02
|-
| rowspan="3" |J1.156138(eMMC on board)| rowspan="3" |NAND_RE_BNAND_DATA00| rowspan="3" |CPU.NAND_RE_BNAND_DATA00| rowspan="3" |K19G20
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_RE_BRAWNAND_DATA00
|-
|ALT1
|QSPI_B_DQSQSPI_A_DATA0
|-
|ALT5
|GPIO3_IO15GPIO3_IO06
|-
| rowspan="2" |J1.158140(NAND on board)| rowspan="2" |NAND_READY_BSD1_DATA1| rowspan="2" |CPU.NAND_READY_BSD1_DATA1| rowspan="2" |K20M24
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|RAWNAND_READY_BUSDHC1_DATA1
|-
|ALT5
|GPIO3_IO16GPIO2_IO0
|-
| rowspan="23" |J1.160140(eMMC on board)| rowspan="23" |NAND_WE_BNAND_DATA01| rowspan="23" |CPU.NAND_WE_BNAND_DATA01| rowspan="23" |K22J20| rowspan="23" |NVCC_3V3| rowspan="23" |I/O| rowspan="23" |
|ALT0
|RAWNAND_WE_BRAWNAND_DATA01|-|ALT1|QSPI_A_DATA1
|-
|ALT5
|GPIO3_IO17GPIO3_IO07
|-
| rowspan="2" |J1.162142(NAND on board)| rowspan="2" |NAND_WP_BSD1_DATA2| rowspan="2" |CPU.NAND_WP_BSD1_DATA2| rowspan="2" |K21N25
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|RAWNAND_WP_BUSDHC1_DATA2
|-
|ALT5
|GPIO3_IO18GPIO2_IO04|-| rowspan="3" |J1.142(eMMC on board)| rowspan="3" |NAND_DATA02| rowspan="3" |CPU.NAND_DATA02| rowspan="3" |H22| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA02
|-
|ALT1|QSPI_A_DATA2|-|ALT5|GPIO3_IO08|-| rowspan="2" |J1.164144(NAND on board)| rowspan="2" |SD1_DATA3| rowspan="2" |CPU.SD1_DATA3| rowspan="2" |P25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA3|-|ALT5|GPIO2_IO05|-| rowspan="3" |J1.144(eMMC on board)| rowspan="3" |NAND_DATA03| rowspan="3" |CPU.NAND_DATA03| rowspan="3" |J21| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA03|-|ALT1|QSPI_A_DATA3|-|ALT5|GPIO3_IO09|-|J1.146|DGND|DGND| -
|<nowiki>-</nowiki>
|G
|
| colspan="2" |
|-
|J1.166
|CLK1_N
|CPU.CLK1_N
|T23
|
|D
|
| colspan="2" |
|-
| rowspan="2" |J1.168148(NAND on board)|CLK1_Prowspan="2" |SD1_DATA4| rowspan="2" |CPU.CLK1_PSD1_DATA4|R23rowspan="2" |N24|rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|Drowspan="2" |I/O| colspanrowspan="2" ||ALT0|USDHC1_DATA4|-|ALT5|GPIO2_IO06
|-
| rowspan="3" |J1.170148(eMMC on board)|USB2_RXNrowspan="3" |NAND_DATA04| rowspan="3" |CPU.USB2_RX_NNAND_DATA04|B8rowspan="3" |L20|rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| colspanrowspan="23" ||ALT0|RAWNAND_DATA04
|-
|J1.172ALT1|USB2_RXP|CPU.USB2_RX_P|A8||D|| colspan="2" |QSPI_B_DATA0
|-
|J1.174ALT5|USB2_TXN|CPU.USB2_TX_N|B9||D|| colspan="2" |GPIO3_IO10
|-
| rowspan="2" |J1.176150(NAND on board)|USB2_TXProwspan="2" |SD1_DATA5| rowspan="2" |CPU.USB2_TX_PSD1_DATA5|A9rowspan="2" |P24|rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|Drowspan="2" |I/O| colspanrowspan="2" ||ALT0|USDHC1_DATA5|-|ALT5|GPIO2_IO07
|-
| rowspan="3" |J1.178150(eMMC on board)|USB1_RXNrowspan="3" |NAND_DATA05| rowspan="3" |CPU.USB1_RX_NNAND_DATA05|B12rowspan="3" |J22|rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| colspanrowspan="23" ||ALT0|RAWNAND_DATA05
|-
|J1.180ALT1|USB1_RXP|CPU.USB1_RX_P|A12||D|| colspan="2" |QSPI_B_DATA1
|-
|J1.182ALT5|USB1_TXN|CPU.USB1_TX_N|B13||D|| colspan="2" |GPIO3_IO11
|-
| rowspan="2" |J1.184152(NAND on board)| rowspan="2" |USB1_TXPSD1_DATA6| rowspan="2" |CPU.USB1_TX_PSD1_DATA6|A13rowspan="2" |R25|rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|Drowspan="2" |I/O| colspanrowspan="2" ||ALT0|USDHC1_DATA6
|-
|J1.186ALT5|USB1_VBUS|CPU.USB1_VBUS|D14| -|S|| colspan="2" |GPIO2_IO08
|-
| rowspan="3" |J1.188152(eMMC on board)|USB2_VBUSrowspan="3" |NAND_DATA06| rowspan="3" |CPU.USB2_VBUSNAND_DATA06|D9rowspan="3" |L19| -rowspan="3" |NVCC_3V3|Srowspan="3" |I/O| colspanrowspan="23" ||ALT0|RAWNAND_DATA06
|-
|J1.190ALT1|DGND|DGND| -|<nowiki>-</nowiki>|G|| colspan="2" |QSPI_B_DATA2
|-
|ALT5|GPIO3_IO12|-| rowspan="2" |J1.192154(NAND on board)|USB1_IDrowspan="2" |SD1_DATA7| rowspan="2" |CPU.USB1_IDSD1_DATA7|C14rowspan="2" |T25|VDD_PHY_3V3rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O|| colspanrowspan="2" ||ALT0|USDHC1_DATA7|-|ALT5|GPIO2_IO09
|-
| rowspan="3" |J1.194154(eMMC on board)|USB2_IDrowspan="3" |NAND_DATA07| rowspan="3" |CPU.USB2_IDNAND_DATA07|C9rowspan="3" |M19|VDD_PHY_3V3rowspan="3" |NVCC_3V3| rowspan="3" |I/O|| colspanrowspan="23" ||ALT0|RAWNAND_DATA07
|-
|J1.196ALT1|USB1_DN|CPU.USB1_DN|B14| -|D|| colspan="2" |QSPI_B_DATA3
|-
|J1.198ALT5|USB1_DP|CPU.USB1_DP|A14| -|D|| colspan="2" |GPIO3_IO13
|-
|J1.200156(NAND on board)|USB2_DPNAND_RE_B|CPU.USB2_DPNAND_RE_B|K19|A10NVCC_3V3| -I/O|DInternally used for NAND, do not connect
|
| colspan="2" |
|-
|J1.202
|USB2_DN
|CPU.USB2_DN
|B10
| -
|D
|
| colspan="2" |
|-
| rowspan="3" |J1.204156(eMMC on board)|DGNDrowspan="3" |NAND_RE_B|DGNDrowspan="3" |CPU.NAND_RE_B| -rowspan="3" |K19|<nowiki>-</nowiki>rowspan="3" |NVCC_3V3|Growspan="3" |I/O| colspanrowspan="23" ||ALT0|RAWNAND_RE_B
|-
|}ALT1 ===Pinout Table J4 pins declaration ==={| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>QSPI_B_DQS! latexfontsize="scriptsize" | Type -! latexfontsize="scriptsize" | NotesALT5! colspan="2" |Alternative FunctionsGPIO3_IO15
|-
|J4J1.1158(NAND on board)|NAND_READY_B|DGNDCPU.NAND_READY_B|DGNDK20| -NVCC_3V3|<nowiki>-<I/nowiki>O|Internally used for NAND, do not connect|G
|
| colspan="2" |
|-
| rowspan="72" |J4J1.2158(eMMC on board)| rowspan="72" |SAI1_RXD7NAND_READY_B| rowspan="72" |CPU.SAI1_RXD7NAND_READY_B| rowspan="72" |G1K20| rowspan="72" |NVCC_3V3| rowspan="72" |I/O| rowspan="72" |internally used for BOOT config
|ALT0
|SAI1_RX_DATA7RAWNAND_READY_B
|-
|ALT1ALT5|SAI6_MCLKGPIO3_IO16
|-
|ALT2J1.160(NAND on board)|NAND_WE_B|CPU.NAND_WE_B|K22|NVCC_3V3|I/O|Internally used for NAND, do not connect||SAI1_TX_SYNC
|-
|ALT3rowspan="2" |J1.160(eMMC on board)| rowspan="2" |NAND_WE_B| rowspan="2" |CPU.NAND_WE_B| rowspan="2" |K22| rowspan="2" |NVCC_3V3|SAI1_TX_DATA4rowspan="2" |I/O|-rowspan="2" ||ALT4ALT0|CORESIGHT_TRACE7RAWNAND_WE_B
|-
|ALT5
|GPIO4_IO09GPIO3_IO17
|-
|ALT6J1.162(NAND on board)|NAND_WP_B|CPU.NAND_WP_B|K21|NVCC_3V3|I/O|Internally used for NAND, do not connect||SRC_BOOT_CFG7
|-
| rowspan="62" |J4J1.3162(eMMC on board)| rowspan="62" |SAI1_RXD6NAND_WP_B| rowspan="62" |CPU.SAI1_RXD6NAND_WP_B| rowspan="62" |G2K21| rowspan="62" |NVCC_3V3| rowspan="62" |I/O| rowspan="62" |internally used for BOOT config
|ALT0
|SAI1_RX_DATA6|-|ALT1|SAI6_TX_SYNC|-|ALT2|SAI6_RX_SYNC|-|ALT4|CORESIGHT_TRACE6RAWNAND_WP_B
|-
|ALT5
|GPIO4_IO08GPIO3_IO18
|-
|ALT6J1.164|DGND|DGND| -|<nowiki>-</nowiki>|G|||SRC_BOOT_CFG6
|-
| rowspan="7" |J4J1.4166| rowspan="7" |SAI1_RXD5CLK1_N| rowspan="7" |CPU.SAI1_RXD5CLK1_N| rowspan="7" |F1T23| rowspan="7" |NVCC_3V3| rowspan="7" |I/OD| rowspan="7" |internally used for BOOT config|ALT0|SAI1_RX_DATA5
|-
|ALT1J1.168|CLK1_P|CPU.CLK1_P|R23||D|||SAI6_TX_DATA0
|-
|ALT2J1.170|USB2_RXN|CPU.USB2_RX_N|B8||D|||SAI6_RX_DATA0
|-
|ALT3J1.172|SAI1_RX_SYNCUSB2_RXP|CPU.USB2_RX_P|A8||D|-|ALT4|CORESIGHT_TRACE5
|-
|ALT5J1.174|USB2_TXN|CPU.USB2_TX_N|B9||D|||GPIO4_IO07
|-
|ALT6J1.176|USB2_TXP|CPU.USB2_TX_P|A9||D|||SRC_BOOT_CFG5
|-
| rowspan="6" |J4J1.5178| rowspan="6" |SAI1_RXD4USB1_RXN| rowspan="6" |CPU.SAI1_RXD4USB1_RX_N| rowspan="6" |J1B12| rowspan="6" |NVCC_3V3| rowspan="6" |I/OD| rowspan="6" |internally used for BOOT config|ALT0|SAI1_RX_DATA4
|-
|ALT1J1.180|USB1_RXP|CPU.USB1_RX_P|A12||D|||SAI6_TX_BCLK
|-
|ALT2J1.182|USB1_TXN|CPU.USB1_TX_N|B13||D|||SAI6_RX_BCLK
|-
|ALT4J1.184|CORESIGHT_TRACE4USB1_TXP|CPU.USB1_TX_P|A13||D|-|ALT5|GPIO4_IO06
|-
|ALT6J1.186|USB1_VBUS|CPU.USB1_VBUS|D14| -|S|Absolute maximum ratings 5.25V||SRC_BOOT_CFG4
|-
| rowspan="5" |J4J1.6188| rowspan="5" |SAI1_RXD3USB2_VBUS| rowspan="5" |CPU.SAI1_RXD3USB2_VBUS| rowspan="5" |J2D9| rowspan="5" |NVCC_3V3-| rowspan="5" |I/OS| rowspan="Absolute maximum ratings 5" |internally used for BOOT config.25V|ALT0|SAI1_RX_DATA3
|-
|ALT1J1.190|SAI5_RX_DATA3DGND|DGND|-|ALT4<nowiki>-</nowiki>|G|||CORESIGHT_TRACE3
|-
|ALT5J1.192|USB1_ID|CPU.USB1_ID|C14|VDD_PHY_3V3|I|||GPIO4_IO05
|-
|ALT6J1.194|USB2_ID|CPU.USB2_ID|C9|VDD_PHY_3V3|I|||SRC_BOOT_CFG3
|-
| rowspan="5" |J4J1.7196| rowspan="5" |SAI1_RXD2USB1_DN| rowspan="5" |CPU.SAI1_RXD2USB1_DN| rowspan="5" |H2B14| rowspan="5" |NVCC_3V3-| rowspan="5" |I/OD| rowspan="5" |internally used for BOOT config|ALT0|SAI1_RX_DATA2
|-
|ALT1J1.198|USB1_DP|CPU.USB1_DP|A14| -|D|||SAI5_RX_DATA2
|-
|ALT4J1.200|USB2_DP|CPU.USB2_DP|A10| -|D|||CORESIGHT_TRACE2
|-
|ALT5J1.202|GPIO4_IO04USB2_DN|CPU.USB2_DN|B10|-|ALT6D|||SRC_BOOT_CFG2
|-
| rowspan="5" |J4J1.8204| rowspan="5" |SAI1_RXD1| rowspan="5" |CPU.SAI1_RXD1DGND| rowspan="5" |L2DGND| rowspan="5" |NVCC_3V3-| rowspan="5" |I<nowiki>-</Onowiki>| rowspan="5" G|internally used for BOOT config|ALT0|SAI1_RX_DATA1
|-
|ALT1} ==ONE PIECE J4 pins declaration =={| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" | Voltage domain! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! colspan="2" |SAI5_RX_DATA1Alternative Functions
|-
|ALT4J4.1|DGND|DGND| -|<nowiki>-</nowiki>|G|||CORESIGHT_TRACE1
|-
|ALT5|GPIO4_IO03|-|ALT6|SRC_BOOT_CFG1|-| rowspan="57" |J4.92| rowspan="57" |SAI1_RXD0SAI1_RXD7| rowspan="57" |CPU.SAI1_RXD0SAI1_RXD7| rowspan="57" |K2G1| rowspan="57" |NVCC_3V3| rowspan="57" |I/O| rowspan="57" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA0SAI1_RX_DATA7
|-
|ALT1
|SAI5_RX_DATA0SAI6_MCLK|-|ALT2|SAI1_TX_SYNC
|-
|ALT3|SAI1_TX_DATA4|-|ALT4|CORESIGHT_TRACE0CORESIGHT_TRACE7
|-
|ALT5
|GPIO4_IO02GPIO4_IO09
|-
|ALT6
|SRC_BOOT_CFG0SRC_BOOT_CFG7
|-
| rowspan="46" |J4.103| rowspan="46" |SAI1_RXCSAI1_RXD6| rowspan="46" |CPU.SAI1_RXCSAI1_RXD6| rowspan="46" |K1G2| rowspan="46" |NVCC_3V3| rowspan="46" |I/O| rowspan="46" |Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_BCLKSAI1_RX_DATA6
|-
|ALT1
|SAI5_RX_BCLKSAI6_TX_SYNC|-|ALT2|SAI6_RX_SYNC
|-
|ALT4
|CORESIGHT_TRACE_CTLCORESIGHT_TRACE6
|-
|ALT5
|GPIO4_IO01GPIO4_IO08|-|ALT6|SRC_BOOT_CFG6
|-
| rowspan="47" |J4.114| rowspan="47" |SAI1_RXFSSAI1_RXD5| rowspan="47" |CPU.SAI1_RXFSSAI1_RXD5| rowspan="47" |L1F1| rowspan="47" |NVCC_3V3| rowspan="47" |I/O| rowspan="47" |Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_SYNCSAI1_RX_DATA5
|-
|ALT1
|SAI5_RX_SYNCSAI6_TX_DATA0|-|ALT2|SAI6_RX_DATA0|-|ALT3|SAI1_RX_SYNC
|-
|ALT4
|CORESIGHT_TRACE_CLKCORESIGHT_TRACE5
|-
|ALT5
|GPIO4_IO00GPIO4_IO07
|-
|J4.12ALT6|DGND|DGND| -|<nowiki>-</nowiki>|G|| colspan="2" |SRC_BOOT_CFG5
|-
| rowspan="46" |J4.135| rowspan="46" |SAI1_MCLKSAI1_RXD4| rowspan="46" |CPU.SAI1_MCLKSAI1_RXD4| rowspan="46" |J1| rowspan="46" |NVCC_3V3| rowspan="46" |I/O| rowspan="46" |Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_MCLKSAI1_RX_DATA4
|-
|ALT1
|SAI5_MCLK SAI6_TX_BCLK
|-
|ALT2
|SAI1_TX_BCLKSAI6_RX_BCLK|-|ALT4|CORESIGHT_TRACE4
|-
|ALT5
|GPIO4_IO20GPIO4_IO06
|-
|J4.14ALT6|DGND|DGND| -|<nowiki>-</nowiki>|G|| colspan="2" |SRC_BOOT_CFG4
|-
| rowspan="45" |J4.156| rowspan="45" |SAI1_TXFSSAI1_RXD3| rowspan="45" |CPU.SAI1_TXFSSAI1_RXD3| rowspan="45" |H4J2| rowspan="45" |NVCC_3V3| rowspan="45" |I/O| rowspan="45" |Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_SYNCSAI1_RX_DATA3
|-
|ALT1
|SAI5_TX_SYNCSAI5_RX_DATA3
|-
|ALT4
|CORESIGHT_EVENTOCORESIGHT_TRACE3
|-
|ALT5
|GPIO4_IO10GPIO4_IO05|-|ALT6|SRC_BOOT_CFG3
|-
| rowspan="45" |J4.167| rowspan="45" |SAI1_TXCSAI1_RXD2| rowspan="45" |CPU.SAI1_TXCSAI1_RXD2| rowspan="45" |J5H2| rowspan="45" |NVCC_3V3| rowspan="45" |I/O| rowspan="45" |Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_BCLKSAI1_RX_DATA2
|-
|ALT1
|SAI5_TX_BCLKSAI5_RX_DATA2
|-
|ALT4
|CORESIGHT_EVENTICORESIGHT_TRACE2
|-
|ALT5
|GPIO4_IO11GPIO4_IO04
|-
|ALT6|SRC_BOOT_CFG2|-| rowspan="5" |J4.178| rowspan="5" |SAI1_TXD0SAI1_RXD1| rowspan="5" |CPU.SAI1_TXD0SAI1_RXD1| rowspan="5" |F2L2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA0SAI1_RX_DATA1
|-
|ALT1
|SAI5_TX_DATA0SAI5_RX_DATA1
|-
|ALT4
|CORESIGHT_TRACE8CORESIGHT_TRACE1
|-
|ALT5
|GPIO4_IO12GPIO4_IO03
|-
|ALT6
|SRC_BOOT_CFG8SRC_BOOT_CFG1
|-
| rowspan="5" |J4.189| rowspan="5" |SAI1_TXD1SAI1_RXD0| rowspan="5" |CPU.SAI1_TXD1SAI1_RXD0| rowspan="5" |E2K2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA1SAI1_RX_DATA0
|-
|ALT1
|SAI5_TX_DATA1SAI5_RX_DATA0
|-
|ALT4
|CORESIGHT_TRACE9CORESIGHT_TRACE0
|-
|ALT5
|GPIO4_IO13GPIO4_IO02
|-
|ALT6
|SRC_BOOT_CFG9SRC_BOOT_CFG0
|-
| rowspan="54" |J4.1910| rowspan="54" |SAI1_TXD2SAI1_RXC| rowspan="54" |CPU.SAI1_TXD2SAI1_RXC| rowspan="54" |B2K1| rowspan="54" |NVCC_3V3| rowspan="54" |I/O| rowspan="54" |internally used for BOOT config
|ALT0
|SAI1_TX_DATA2SAI1_RX_BCLK
|-
|ALT1
|SAI5_TX_DATA2SAI5_RX_BCLK
|-
|ALT4
|CORESIGHT_TRACE10CORESIGHT_TRACE_CTL
|-
|ALT5
|GPIO4_IO14GPIO4_IO01
|-
|ALT6|SRC_BOOT_CFG10|-| rowspan="54" |J4.2011| rowspan="54" |SAI1_TXD3SAI1_RXFS| rowspan="54" |CPU.SAI1_TXD3SAI1_RXFS| rowspan="54" |D1L1| rowspan="54" |NVCC_3V3| rowspan="54" |I/O| rowspan="54" |internally used for BOOT config
|ALT0
|SAI1_TX_DATA3SAI1_RX_SYNC
|-
|ALT1
|SAI5_TX_DATA3SAI5_RX_SYNC
|-
|ALT4
|CORESIGHT_TRACE11CORESIGHT_TRACE_CLK
|-
|ALT5
|GPIO4_IO15GPIO4_IO00
|-
|ALT6J4.12|DGND|DGND| -|<nowiki>-</nowiki>|G|||SRC_BOOT_CFG11
|-
| rowspan="64" |J4.2113| rowspan="64" |SAI1_TXD4SAI1_MCLK| rowspan="64" |CPU.SAI1_TXD4SAI1_MCLK| rowspan="64" |D2| rowspan="64" |NVCC_3V3| rowspan="64" |I/O| rowspan="64" |internally used for BOOT config
|ALT0
|SAI1_TX_DATA4SAI1_MCLK
|-
|ALT1
|SAI6_RX_BCLKSAI5_MCLK
|-
|ALT2
|SAI6_TX_BCLK|-|ALT4|CORESIGHT_TRACE12SAI1_TX_BCLK
|-
|ALT5
|GPIO4_IO16GPIO4_IO20
|-
|ALT6J4.14|DGND|DGND| -|<nowiki>-</nowiki>|G|||SRC_BOOT_CFG12
|-
| rowspan="64" |J4.2215| rowspan="64" |SAI1_TXD5SAI1_TXFS| rowspan="64" |CPU.SAI1_TXD5SAI1_TXFS| rowspan="64" |C2H4| rowspan="64" |NVCC_3V3| rowspan="64" |I/O| rowspan="64" |internally used for BOOT config
|ALT0
|SAI1_TX_DATA5SAI1_TX_SYNC
|-
|ALT1
|SAI6_RX_DATA0|-|ALT2|SAI6_TX_DATA0SAI5_TX_SYNC
|-
|ALT4
|CORESIGHT_TRACE13CORESIGHT_EVENTO
|-
|ALT5
|GPIO4_IO17GPIO4_IO10
|-
|ALT6|SRC_BOOT_CFG13|-| rowspan="64" |J4.2316| rowspan="64" |SAI1_TXD6SAI1_TXC| rowspan="64" |CPU.SAI1_TXD6SAI1_TXC| rowspan="64" |B3J5| rowspan="64" |NVCC_3V3| rowspan="64" |I/O| rowspan="64" |internally used for BOOT config
|ALT0
|SAI1_TX_DATA6SAI1_TX_BCLK
|-
|ALT1
|SAI6_RX_SYNC|-|ALT2|SAI6_TX_SYNCSAI5_TX_BCLK
|-
|ALT4
|CORESIGHT_TRACE14CORESIGHT_EVENTI
|-
|ALT5
|GPIO4_IO18GPIO4_IO11
|-
|ALT6|SRC_BOOT_CFG14|-| rowspan="5" |J4.2417| rowspan="5" |SAI1_TXD7SAI1_TXD0| rowspan="5" |CPU.SAI1_TXD7SAI1_TXD0| rowspan="5" |C1F2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA7SAI1_TX_DATA0
|-
|ALT1
|SAI6_MCLKSAI5_TX_DATA0
|-
|ALT4
|CORESIGHT_TRACE15CORESIGHT_TRACE8
|-
|ALT5
|GPIO4_IO19GPIO4_IO12
|-
|ALT6
|SRC_BOOT_CFG15SRC_BOOT_CFG8|-| rowspan="5" |J4.18| rowspan="5" |SAI1_TXD1| rowspan="5" |CPU.SAI1_TXD1| rowspan="5" |E2| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_TX_DATA1
|-
|J4.25ALT1|DGND|DGND| -|<nowiki>-</nowiki>|G|| colspan="2" ||}===Pinout Table J5 pins declaration ==={| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! latexfontsize="scriptsize" | Alternative FunctionsSAI5_TX_DATA1
|-
|J5.1ALT4|DGND|DGND| -|<nowiki>-</nowiki>|G| colspan="2" |CORESIGHT_TRACE9
|-
|J5.2ALT5|PCIE2_RXN|CPU.PCIE2_RXN_N|D24| -|D| colspan="2" |GPIO4_IO13
|-
|J5.3ALT6|PCIE2_RXP|CPU.PCIE2_RXN_P|D25| -|D| colspan="2" |SRC_BOOT_CFG9
|-
|J5rowspan="5" |J4.419|DGNDrowspan="5" |SAI1_TXD2|DGNDrowspan="5" |CPU.SAI1_TXD2| -rowspan="5" |B2|<nowiki>-</nowiki>rowspan="5" |NVCC_3V3|Growspan="5" |I/O| colspanrowspan="25" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_TX_DATA2
|-
|J5.5ALT1|PCIE2_TXN|CPU.PCIE2_TXN_N|E24| -|D| colspan="2" |SAI5_TX_DATA2
|-
|J5.6ALT4|PCIE2_TXP|CPU.PCIE2_TXN_P|E25| -|D| colspan="2" |CORESIGHT_TRACE10
|-
|J5.7ALT5|DGND|DGND| -|<nowiki>-</nowiki>|G| colspan="2" |GPIO4_IO14
|-
|J5.8ALT6|PCIE2_REF_CLKN|CPU.PCIE2_REF_PAD_CLK_N|F24| -|D| colspan="2" |SRC_BOOT_CFG10
|-
|J5rowspan="5" |J4.920|PCIE2_REF_CLKProwspan="5" |SAI1_TXD3| rowspan="5" |CPU.PCIE2_REF_PAD_CLK_PSAI1_TXD3|F25rowspan="5" |D1| -rowspan="5" |NVCC_3V3|Drowspan="5" |I/O| colspanrowspan="25" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_TX_DATA3
|-
|J5.10ALT1|DGND|DGND| -|<nowiki>-</nowiki>|G| colspan="2" |SAI5_TX_DATA3
|-
|J5.11ALT4|CSI_P2_CKN|CPU.MIPI_CSI2_CLK_N|A19| -|D| colspan="2" |CORESIGHT_TRACE11
|-
|J5.12ALT5|CSI_P2_CKP|CPU.MIPI_CSI2_CLK_P|B19| -|D| colspan="2" |GPIO4_IO15
|-
|J5.13ALT6|DGND|DGND| -|<nowiki>-</nowiki>|G| colspan="2" |SRC_BOOT_CFG11
|-
|J5rowspan="6" |J4.1421|CSI_P2_DN0rowspan="6" |SAI1_TXD4| rowspan="6" |CPU.MIPI_CSI2_D0_NSAI1_TXD4|C20rowspan="6" |D2| -rowspan="6" |NVCC_3V3|Drowspan="6" |I/O| colspanrowspan="26" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_TX_DATA4
|-
|J5.15ALT1|CSI_P2_DP0|CPU.MIPI_CSI2_D0_P|D10| -|D| colspan="2" |SAI6_RX_BCLK
|-
|J5.16ALT2|CSI_P2_DN1|CPU.MIPI_CSI2_D1_N|A20| -|D| colspan="2" |SAI6_TX_BCLK
|-
|J5.17ALT4|CSI_P2_DP1|CPU.MIPI_CSI2_D1_P|B20| -|D| colspan="2" |CORESIGHT_TRACE12
|-
|J5.18ALT5|DGND|DGND| -|<nowiki>-</nowiki>|G| colspan="2" |GPIO4_IO16
|-
|J5.19ALT6|CSI_P2_DN2|CPU.MIPI_CSI2_D2_N|A21| -|D| colspan="2" |SRC_BOOT_CFG12
|-
|J5rowspan="6" |J4.2022|CSI_P2_DP2rowspan="6" |SAI1_TXD5| rowspan="6" |CPU.MIPI_CSI2_D2_PSAI1_TXD5|B21rowspan="6" |C2| -rowspan="6" |NVCC_3V3|Drowspan="6" |I/O| colspanrowspan="26" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_TX_DATA5
|-
|J5.21ALT1|CSI_P2_DN3|CPU.MIPI_CSI2_D3_N|C19| -|D| colspan="2" |SAI6_RX_DATA0
|-
|J5.22ALT2|CSI_P2_DP3SAI6_TX_DATA0|CPU.MIPI_CSI2_D3_P-|ALT4|D19CORESIGHT_TRACE13| -|DALT5| colspan="2" |GPIO4_IO17
|-
|J5.23ALT6|DGND|DGND| -|<nowiki>-</nowiki>|G| colspan="2" |SRC_BOOT_CFG13
|-
| rowspan="46" |J5J4.2423| rowspan="46" |I2C4_SCLSAI1_TXD6| rowspan="46" |CPU.I2C4_SCLSAI1_TXD6| rowspan="46" |F8B3| rowspan="46" |NVCC_3V3| rowspan="46" |I/O| rowspan="6" |Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|I2C4_SCLSAI1_TX_DATA6
|-
|ALT1
|PWM2_OUTSAI6_RX_SYNC
|-
|ALT2
|PCIE1_CLKREQ_BSAI6_TX_SYNC|-|ALT4|CORESIGHT_TRACE14
|-
|ALT5
|GPIO5_IO20GPIO4_IO18|-|ALT6|SRC_BOOT_CFG14
|-
| rowspan="45" |J5J4.2524| rowspan="45" |I2C4_SDASAI1_TXD7| rowspan="45" |CPU.I2C4_SDASAI1_TXD7| rowspan="45" |F9C1| rowspan="45" |NVCC_3V3| rowspan="45" |I/O| rowspan="5" |Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|I2C4_SDASAI1_TX_DATA7
|-
|ALT1
|PWM1_OUTSAI6_MCLK
|-
|ALT2ALT4|PCIE2_CLKREQ_BCORESIGHT_TRACE15
|-
|ALT5
|GPIO5_IO21GPIO4_IO19|-|ALT6|SRC_BOOT_CFG15|-|J4.25|DGND|DGND| -|<nowiki>-</nowiki>|G||||} ===Pinout Table JD5 ONE PIECE J5 pins declaration ==={| class="wikitable" ! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
! latexfontsizecolspan="scriptsize2" | Alternative Functions
|-
|JD5J5.1
|DGND
|DGND
|<nowiki>-</nowiki>
|G
|
|
|
|-
|JD5J5.2|EEPROM_WPPCIE2_RXN|Internal EEPROM Write ProtectCPU.PCIE2_RXN_N|D24
| -
|NVCC_3V3D|I
|
|
|-
|JD5J5.3|NCPCIE2_RXP|Not ConnectedCPU.PCIE2_RXN_P|D25
| -
| -|ZD
|
|
|-
|JD5.4
|JTAG_TCK
|CPU.JTAG_TCK
|T5
|NVCC_3V3
|I
|internal pull-up 10k to NVCC_3V3
|
|-
|JD5J5.54|JTAG_TMSDGND|CPU.JTAG_TMSDGND| -|V5<nowiki>-</nowiki>|NVCC_3V3G|I
|
|
|-
|JD5J5.65|JTAG_TDOPCIE2_TXN|CPU.JTAG_TDOPCIE2_TXN_N|U5E24|NVCC_3V3-|OD
|
|
|-
|JD5.7
|JTAG_TDI
|CPU.JTAG_TDI
|W5
|NVCC_3V3
|I
|
|
|-
|JD5J5.86|JTAG_nTRSTPCIE2_TXP|CPU.JTAG_TRST_BPCIE2_TXN_P|U6E25|NVCC_3V3-|ID
|
|
|-
|JD5.9
|CPU_PORn
|CPU.POR_B
PMIC.RESETMCU
|W20
3
|NVCC_SNVS
|I/O
|internal pull-up 100k to NVCC_SNVS
|
|-
|JD5J5.107|NVCC_3V3DGND|NVCC_3V3DGND
| -
|<nowiki>-</nowiki>
|SG||||-|J5.8|PCIE2_REF_CLKN|CPU.PCIE2_REF_PAD_CLK_N|F24| -|D||||-|J5.9|PCIE2_REF_CLKP|CPU.PCIE2_REF_PAD_CLK_P|F25| -|D||||-|J5.10|DGND|DGND| -|<nowiki>-</nowiki>|G|
|
|
|-
|J5.11
|CSI_P2_CKN
|CPU.MIPI_CSI2_CLK_N
|A19
| -
|D
|
|
|
|-
|J5.12
|CSI_P2_CKP
|CPU.MIPI_CSI2_CLK_P
|B19
| -
|D
|
|
|
|-
|J5.13
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.14
|CSI_P2_DN0
|CPU.MIPI_CSI2_D0_N
|C20
| -
|D
|
|
|
|-
|J5.15
|CSI_P2_DP0
|CPU.MIPI_CSI2_D0_P
|D10
| -
|D
|
|
|
|-
|J5.16
|CSI_P2_DN1
|CPU.MIPI_CSI2_D1_N
|A20
| -
|D
|
|
|
|-
|J5.17
|CSI_P2_DP1
|CPU.MIPI_CSI2_D1_P
|B20
| -
|D
|
|
|
|-
|J5.18
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.19
|CSI_P2_DN2
|CPU.MIPI_CSI2_D2_N
|A21
| -
|D
|
|
|
|-
|J5.20
|CSI_P2_DP2
|CPU.MIPI_CSI2_D2_P
|B21
| -
|D
|
|
|
|-
|J5.21
|CSI_P2_DN3
|CPU.MIPI_CSI2_D3_N
|C19
| -
|D
|
|
|
|-
|J5.22
|CSI_P2_DP3
|CPU.MIPI_CSI2_D3_P
|D19
| -
|D
|
|
|
|-
|J5.23
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
| rowspan="4" |J5.24
| rowspan="4" |I2C4_SCL
| rowspan="4" |CPU.I2C4_SCL
| rowspan="4" |F8
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|I2C4_SCL
|-
|ALT1
|PWM2_OUT
|-
|ALT2
|PCIE1_CLKREQ_B
|-
|ALT5
|GPIO5_IO20
|-
| rowspan="4" |J5.25
| rowspan="4" |I2C4_SDA
| rowspan="4" |CPU.I2C4_SDA
| rowspan="4" |F9
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|I2C4_SDA
|-
|ALT1
|PWM1_OUT
|-
|ALT2
|PCIE2_CLKREQ_B
|-
|ALT5
|GPIO5_IO21
|}
U0007
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