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MITO 8M SOM/MITO 8M Hardware/Pinout Table

4,441 bytes added, 17:49, 28 December 2023
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<section begin="History" />
{| style="border-collapse:collapse; "
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
|-
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0{{oldid| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" 10368|Sep 2020/09/29}}
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |2021/02/02
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |Add pull-up/down information
|-
|}
<section end="History" /><section begin="Body" />==Connectors and Pinout Table=====Introduction=description==
This chapter contains the pinout === Connectors description of ===In the following table are described all available connectors integrated on MITO 8M module, grouped in two tables (odd and even pins) that report the SOM:{| class="wikitable"|-!Connector name!Connector Type!Notes!Carrier board counterpart|-|J1|SODIMM edge connector 204 pin mapping of the 204|partially compatible with [[AXEL Lite SOM]]|TE Connectivity 2-2013289-1|-|J4|ONE PIECE connector single row 25pins||SAMTEC FSI-125-03-G-S-AD-TR|-|J5|ONE PIECE connector single row 25pins||SAMTEC FSI-125-03-G-S-pin SOAD-DIMM TR|}The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to MITO 8M connectorpinout specifications.See the images below for reference:
[[File:MITO 8M-conn-TOP.png|500px|thumb|MITO 8M TOP view|none]]
[[File:MITO 8M-conn-BOTTOM.png|500px|thumb|MITO 8M BOTTOM view|none]]
 
Below a detailed description of the pinout, grouped in the following tables:
* two tables (ODD and EVEN pins) that report the pin mapping of the 204-pin SO-DIMM edge
* a dedicated tables for J4 one-piece connector
* a dedicated tables for J5 one-piece connector
 
=== Pinout Table description ===
Each row in the pinout tables contains the following information:
 {| class="wikitable" style="width:50%;"
|-
|'''Pin'''
|-
|'''Pin Name'''
| Pin (signal) name on the AxelLite MITO 8M connectors
|-
|'''Internal<br>connections'''
| Connections to the Axel Ultra components
* CPU.<x> : pin connected to CPU pad named <x>
* PMIC.<x> : pin connected to the Power Manager IC(NXP PF4210)* LAN.<x> : pin connected to the LAN PHY(MICROCHIP KSZ9031RNX)* BRIDGE.<x> : pin connected to the MIPI-to-LVDS bridge* SV.<x>: pin connected to voltage supervisor(TI SN65DSI84)
|-
|'''Ball/pin #'''
|}
===Pinout Table SODIMM J1 ODD pins declaration ===
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| colspan="2" |
|-
|J1.3
|S
|
| colspan="2" |
|-
|J1.5
|S
|
| colspan="2" |
|-
|J1.7
|S
|
| colspan="2" |
|-
|J1.9
|S
|
| colspan="2" |
|-
|J1.11
|G
|
| colspan="2" |
|-
|J1.13
|NVCC_1V8
|I/O
|must Must be level translated if used @ 3V3Internally pulled-up to 1.8V during bootstrap| colspan="2" |
|-
|J1.15
|NVCC_1V8
|I/O
|must Must be level translated if used @ 3V3Internally pulled-up to 1.8V during bootstrap| colspan="2" |
|-
|J1.17
|G
|
| colspan="2" |
|-
|J1.19
|D
|
| colspan="2" |
|-
|J1.21
|D
|
| colspan="2" |
|-
|J1.23
|D
|
| colspan="2" |
|-
|J1.25
|D
|
| colspan="2" |
|-
|J1.27
|D
|
| colspan="2" |
|-
|J1.29
|D
|
| colspan="2" |
|-
|J1.31
|D
|
| colspan="2" |
|-
|J1.33
|D
|
| colspan="2" |
|-
|J1.35
|G
|
| colspan="2" |
|-
| rowspan="4" |J1.37
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for ETH PHY reset, do not connect
|ALT0
|GPIO1_IO01
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |Internally used, do not connect
|ALT0
|GPIO1_IO13
|
|
| colspan="2" |
|-
| rowspan="3" |J1.47
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| colspan="2" |
|-
| rowspan="3" |J1.59
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |Internally used for MIPI-to-LVDS interrupt, do not connectPulled-up to NVCC_3V3
|ALT0
|GPIO1_IO05
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for MIPI-to-LVDS enable, do not connect
|ALT0
|GPIO1_IO06
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| colspan="2" |
|-
| rowspan="2" |J1.75
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| colspan="2" |
|-
| rowspan="3" |J1.89
|I/O
|
| colspan="2" |
|-
|J1.103
|I/O
|
| colspan="2" |
|-
|J1.105
|D
|connected with capacitor in series
| colspan="2" |
|-
|J1.107
|D
|connected with capacitor in series
| colspan="2" |
|-
|J1.109
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| colspan="2" |
|-
|J1.111
|D
|connected with capacitor in series
| colspan="2" |
|-
|J1.113
|D
|connected with capacitor in series
| colspan="2" |
|-
|J1.115
|D
|connected with capacitor in series
| colspan="2" |
|-
|J1.117
|D
|connected with capacitor in series
| colspan="2" |
|-
|J1.119
|D
|connected with capacitor in series
| colspan="2" |
|-
|J1.121
|D
|connected with capacitor in series
| colspan="2" |
|-
|J1.123
|D
|connected with capacitor in series
| colspan="2" |
|-
|J1.125
|D
|connected with capacitor in series
| colspan="2" |
|-
|J1.127
|I/O
|
| colspan="2" |
|-
|J1.129
|I/O
|
| colspan="2" |
|-
|J1.131
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| colspan="2" |
|-
|J1.133
|D
|
| colspan="2" |
|-
|J1.135
|D
|
| colspan="2" |
|-
|J1.137
|D
|
| colspan="2" |
|-
|J1.139
|D
|
| colspan="2" |
|-
|J1.141
|D
|
| colspan="2" |
|-
|J1.143
|D
|
| colspan="2" |
|-
|J1.145
|D
|
| colspan="2" |
|-
|J1.147
|D
|
| colspan="2" |
|-
|J1.149
|D
|
| colspan="2" |
|-
|J1.151
|D
|
| colspan="2" |
|-
|J1.153
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| colspan="2" |
|-
|J1.155
|D
|
| colspan="2" |
|-
|J1.157
|D
|
| colspan="2" |
|-
|J1.159
|D
|
| colspan="2" |
|-
|J1.161
|D
|
| colspan="2" |
|-
|J1.163
|D
|
| colspan="2" |
|-
|J1.165
|D
|
| colspan="2" |
|-
|J1.167
|D
|
| colspan="2" |
|-
|J1.169
|D
|
| colspan="2" |
|-
|J1.171
|D
|
| colspan="2" |
|-
|J1.173
|D
|
| colspan="2" |
|-
|J1.175
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| colspan="2" |
|-
| rowspan="2" |J1.177
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="63" |used as default Linux console
|ALT0
|UART2_TX
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |used as default Linux console
|ALT0
|UART2_RXD
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| colspan="2" |
|-
|}
===Pinout Table SODIMM J1 EVEN pins declaration ===
{| class="wikitable"
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
|G
|
| colspan="2" |
|-
|J1.4
|S
|
| colspan="2" |
|-
|J1.6
|S
|
| colspan="2" |
|-
|J1.8
|S
|
| colspan="2" |
|-
|J1.10
|S
|
| colspan="2" |
|-
|J1.12
|G
|
| colspan="2" |
|-
|J1.14
|S
|
| colspan="2" |
|-
|J1.16
|I
|internal pull-up 100k to NVCC_SNVS
| colspan="2" |
|-
|J1.18
|O
|
| colspan="2" |
|-
|J1.20
|I
|internal pull-up to NVCC_3V3
| colspan="2" |
|-
|J1.22
|I/O
|internal pull-up 100k to NVCC_SNVS
| colspan="2" |
|-
|J1.24
|I
|internal pull-up to NVCC_SNVS
| colspan="2" |
|-
| rowspan="4" |J1.26
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for SW reset, do not connect
|ALT0
|GPIO1_IO02
|G
|
| colspan="2" |
|-
| rowspan="4" |J1.32
|-
| rowspan="2" |J1.54
| rowspan="2" |SD1_STROBEGPIO1_IO10| rowspan="2" |CPU.SD1_STROBEGPIO1_IO10| rowspan="2" |T24M7| rowspan="2" |NVCC_1V8(NVCC_3V3 on request)
| rowspan="2" |I/O
| rowspan="2" |internally Internally used for eMMC(available on NAND storage SOM) ???ETH PHY interrupt, do not connect
|ALT0
|USDHC1_STROBE GPIO1_IO10
|-
|ALT5ALT1|GPIO2_IO11USB1_OTG_ID
|-
|J1.56
|G
|
| colspan="2" |
|-
| rowspan="4" |J1.58
|G
|
| colspan="2" |
|-
|J1.84
|VDDA_1V8
|D
|Internally used for PCIe CLK, do not connect
|
|
| colspan="2" |
|-
|J1.86
|VDDA_1V8
|D
|Internally used for PCIe CLK, do not connect
|
|
| colspan="2" |
|-
|J1.88
|D
|
| colspan="2" |
|-
|J1.90
|D
|
| colspan="2" |
|-
|J1.92
|D
|
| colspan="2" |
|-
|J1.94
|D
|
| colspan="2" |
|-
|J1.96
|D
|
| colspan="2" |
|-
|J1.98
|D
|
| colspan="2" |
|-
|J1.100
|G
|
| colspan="2" |
|-
|J1.102
|D
|
| colspan="2" |
|-
|J1.104
|D
|
| colspan="2" |
|-
|J1.106
|D
|
| colspan="2" |
|-
|J1.108
|D
|
| colspan="2" |
|-
|J1.110
|D
|
| colspan="2" |
|-
|J1.112
|D
|
| colspan="2" |
|-
|J1.114
|D
|
| colspan="2" |
|-
|J1.116
|D
|
| colspan="2" |
|-
|J1.118
|D
|
| colspan="2" |
|-
|J1.120
|D
|
| colspan="2" |
|-
|J1.122
|G
|
| colspan="2" ||-|J1.124(NAND on board)|NAND_DQS|CPU.NAND_DQS|M20|NVCC_3V3|I/O|Internally used for NAND, do not connect||
|-
| rowspan="3" |J1.124
(eMMC on board)
| rowspan="3" |NAND_DQS
| rowspan="3" |CPU.NAND_DQS
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |internally used for NAND
|ALT0
|RAWNAND_DQS
|ALT5
|GPIO3_IO14
|-
|J1.126
(NAND on board)
|NAND_ALE
|CPU.NAND_ALE
|G19
|NVCC_3V3
|I/O
|Internally used for NAND, do not connect
|
|
|-
| rowspan="3" |J1.126
(eMMC on board)
| rowspan="3" |NAND_ALE
| rowspan="3" |CPU.NAND_ALE
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |internally used for NAND
|ALT0
|RAWNAND_ALE
|-
|ALT1
|QSPI_A_SCLK
|-
|ALT5
|GPIO3_IO00
|-
| rowspan="2" |J1.128(NAND on board)| rowspan="2" |NAND_CE0_B // SD1_CLK|CPU.NAND_CE0_B // rowspan="2" |CPU.SD1_CLK|H19 // rowspan="2" |L25|rowspan="2" |NVCC_3V3(NVCC_1V8 // NVCC_3V3 ???on request)| rowspan="2" |I/O|???rowspan="2" ||ALT0|USDHC1_CLK
|-
|ALT5||||||||GPIO2_IO00
|-
| rowspan="3" |J1.130128(eMMC on board)|NAND_CE1_B // SD1_CMDrowspan="3" |NAND_CE0_B| rowspan="3" |CPU.NAND_CE1_B // CPU.SD1_CMDNAND_CE0_B|G21 // L24rowspan="3" |H19|NVCC_1V8 // rowspan="3" |NVCC_3V3 ???| rowspan="3" |I/O|???rowspan="3" ||ALT0|RAWNAND_CE0_B
|-
|J1.132|NAND_CE2_B // SD1_RST_B|CPU.NAND_CE2_B // CPU.SD1_RST_B|F21 // R24|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT1|QSPI_A_SS0_B
|-
|J1.134|NAND_CE3_B // SD1_STROBE|CPU.NAND_CE3_B // CPU.SD1_STROBE|H20 // T24|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT5|GPIO3_IO01
|-
| rowspan="2" |J1.136130(NAND on board)|NAND_CLErowspan="2" |SD1_CMD|DGNDrowspan="2" |CPU.SD1_CMD|H21rowspan="2" |L24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_CMD
|-
|J1.138|NAND_DATA00 // SD1_DATA0|CPU.NAND_DATA00 // CPU.SD1_DATA0|G20 // M25|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT5|GPIO2_IO01
|-
| rowspan="3" |J1.140130(eMMC on board)|NAND_DATA01 // SD1_DATA1rowspan="3" |NAND_CE1_B| rowspan="3" |CPU.NAND_DATA01 // CPU.SD1_DATA1NAND_CE1_B|J20 // M24rowspan="3" |G21|NVCC_1V8 // rowspan="3" |NVCC_3V3 ???| rowspan="3" |I/O|???rowspan="3" ||ALT0|RAWNAND_CE1_B
|-
|J1.142|NAND_DATA02 // SD1_DATA2|CPU.NAND_DATA02 // CPU.SD1_DATA2|H22 // N25|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT1|QSPI_A_SS1_B
|-
|J1.144|NAND_DATA03 // SD1_DATA3|CPU.NAND_DATA03 // CPU.SD1_DATA3|J21 // P25|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT5|GPIO3_IO02
|-
| rowspan="2" |J1.146132(NAND on board)| rowspan="2" |SD1_RST_B|DGNDrowspan="2" |CPU.SD1_RST_B|DGNDrowspan="2" |R24| -rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|<nowiki>-<rowspan="2" |I/nowiki>O|Growspan="2" ||ALT0|USDHC1_RESET_B
|-
|J1.148|NAND_DATA04 // SD1_DATA4|CPU.NAND_DATA04 // CPU.SD1_DATA4|L20 // N24|NVCC_1V8 // NVCC_3V3 ???|I/O|???|||-|J1.150|NAND_DATA05 // SD1_DATA5|CPU.NAND_DATA05 // CPU.SD1_DATA5|J22 // P24|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT5|GPIO2_IO10
|-
|J1.152|NAND_DATA06 // SD1_DATA6|CPU.NAND_DATA06 // CPU.SD1_DATA6|L19 // R25|NVCC_1V8 // NVCC_3V3 ???|I/O|???|||-|J1.154|NAND_DATA07 // SD1_DATA7|CPU.NAND_DATA07 // CPU.SD1_DATA7|M19 // T25|NVCC_1V8 // NVCC_3V3 ???|I/O|???|||-| rowspan="3" |J1.156132(eMMC on board)| rowspan="3" |NAND_RE_BNAND_CE2_B| rowspan="3" |CPU.NAND_RE_BNAND_CE2_B| rowspan="3" |K19F21
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_RE_BRAWNAND_CE2_B
|-
|ALT1
|QSPI_B_DQSQSPI_B_SS0_B
|-
|ALT5
|GPIO3_IO15GPIO3_IO03
|-
| rowspan="2" |J1.158134(NAND on board)| rowspan="2" |NAND_READY_BSD1_STROBE| rowspan="2" |CPU.NAND_READY_BSD1_STROBE| rowspan="2" |K20T24
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|RAWNAND_READY_BUSDHC1_STROBE
|-
|ALT5
|GPIO3_IO16GPIO2_IO11
|-
| rowspan="23" |J1.160134(eMMC on board)| rowspan="23" |NAND_WE_BNAND_CE3_B| rowspan="23" |CPU.NAND_WE_BNAND_CE3_B| rowspan="23" |K22H20| rowspan="23" |NVCC_3V3| rowspan="23" |I/O| rowspan="23" |
|ALT0
|RAWNAND_WE_BRAWNAND_CE3_B
|-
|ALT5ALT1|GPIO3_IO17|-| rowspan="2" |J1.162| rowspan="2" |NAND_WP_B| rowspan="2" |CPU.NAND_WP_B| rowspan="2" |K21| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|RAWNAND_WP_BQSPI_B_SS1_B
|-
|ALT5
|GPIO3_IO18GPIO3_IO034
|-
|J1.164136(NAND on board)|DGNDNAND_CLE|DGNDCPU.NAND_CLE| -H21|<nowiki>-<NVCC_3V3|I/nowiki>O|Internally used for NAND, do not connect|G
|
| colspan="2" |
|-
| rowspan="3" |J1.166136(eMMC on board)|CLK1_Nrowspan="3" |NAND_CLE| rowspan="3" |CPU.CLK1_NNAND_CLE|T23rowspan="3" |H21|rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| colspanrowspan="23" ||ALT0|RAWNAND_CLE
|-
|J1.168ALT1|CLK1_P|CPU.CLK1_P|R23||D|| colspan="2" |QSPI_B_SCLK
|-
|J1.170ALT5|USB2_RXN|CPU.USB2_RX_N|B8||D|| colspan="2" |GPIO3_IO05
|-
| rowspan="2" |J1.172138(NAND on board)| rowspan="2" |USB2_RXPSD1_DATA0| rowspan="2" |CPU.USB2_RX_PSD1_DATA0|A8rowspan="2" |M25|rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|Drowspan="2" |I/O| colspanrowspan="2" ||ALT0|USDHC1_DATA0
|-
|J1.174ALT5|USB2_TXN|CPU.USB2_TX_N|B9||D|| colspan="2" |GPIO2_IO02
|-
| rowspan="3" |J1.176138(eMMC on board)|USB2_TXProwspan="3" |NAND_DATA00| rowspan="3" |CPU.USB2_TX_PNAND_DATA00|A9rowspan="3" |G20|rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| colspanrowspan="23" ||ALT0|RAWNAND_DATA00
|-
|J1.178ALT1|USB1_RXN|CPU.USB1_RX_N|B12||D|| colspan="2" |QSPI_A_DATA0
|-
|J1.180ALT5|USB1_RXP|CPU.USB1_RX_P|A12||D|| colspan="2" |GPIO3_IO06
|-
| rowspan="2" |J1.182140(NAND on board)| rowspan="2" |USB1_TXNSD1_DATA1| rowspan="2" |CPU.USB1_TX_NSD1_DATA1|B13rowspan="2" |M24|rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|Drowspan="2" |I/O| colspanrowspan="2" ||ALT0|USDHC1_DATA1
|-
|J1.184ALT5|USB1_TXP|CPU.USB1_TX_P|A13||D|| colspan="2" |GPIO2_IO0
|-
| rowspan="3" |J1.186140(eMMC on board)|USB1_VBUSrowspan="3" |NAND_DATA01| rowspan="3" |CPU.USB1_VBUSNAND_DATA01|D14rowspan="3" |J20| -rowspan="3" |NVCC_3V3|Srowspan="3" |I/O| colspanrowspan="23" ||ALT0|RAWNAND_DATA01
|-
|J1.188ALT1|USB2_VBUS|CPU.USB2_VBUS|D9| -|S|| colspan="2" |QSPI_A_DATA1
|-
|J1.190ALT5|DGND|DGND| -|<nowiki>-</nowiki>|G|| colspan="2" |GPIO3_IO07
|-
| rowspan="2" |J1.192142(NAND on board)|USB1_IDrowspan="2" |SD1_DATA2| rowspan="2" |CPU.USB1_IDSD1_DATA2|C14rowspan="2" |N25|VDD_PHY_3V3rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O|| colspanrowspan="2" ||ALT0|USDHC1_DATA2
|-
|J1.194ALT5|USB2_ID|CPU.USB2_ID|C9|VDD_PHY_3V3|I|| colspan="2" |GPIO2_IO04
|-
| rowspan="3" |J1.196142(eMMC on board)|USB1_DNrowspan="3" |NAND_DATA02| rowspan="3" |CPU.USB1_DNNAND_DATA02|B14rowspan="3" |H22| -rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| colspanrowspan="23" ||ALT0|RAWNAND_DATA02|-|ALT1|QSPI_A_DATA2
|-
|J1.198ALT5|USB1_DP|CPU.USB1_DP|A14| -|D|| colspan="2" |GPIO3_IO08
|-
| rowspan="2" |J1.200144(NAND on board)| rowspan="2" |USB2_DPSD1_DATA3| rowspan="2" |CPU.USB2_DPSD1_DATA3|A10rowspan="2" |P25| -rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|Drowspan="2" |I/O| colspanrowspan="2" ||ALT0|USDHC1_DATA3
|-
|J1.202ALT5|USB2_DN|CPU.USB2_DN|B10| -|D|| colspan="2" |GPIO2_IO05
|-
| rowspan="3" |J1.204144(eMMC on board)|DGNDrowspan="3" |NAND_DATA03|DGNDrowspan="3" |CPU.NAND_DATA03| -rowspan="3" |J21|<nowiki>-</nowiki>rowspan="3" |NVCC_3V3|Growspan="3" |I/O| colspanrowspan="23" ||ALT0|RAWNAND_DATA03|-|ALT1|QSPI_A_DATA3
|-
|}ALT5 ===Pinout Table J4 pins declaration ==={| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! colspan="2" |Alternative FunctionsGPIO3_IO09
|-
|J4J1.1146
|DGND
|DGND
|G
|
| colspan="2" |
|-
| rowspan="72" |J4J1.2148(NAND on board)| rowspan="72" |SAI1_RXD7SD1_DATA4| rowspan="72" |CPU.SAI1_RXD7SD1_DATA4| rowspan="72" |G1N24| rowspan="72" |NVCC_3V3(NVCC_1V8 on request)| rowspan="72" |I/O| rowspan="72" |internally used for BOOT config
|ALT0
|SAI1_RX_DATA7USDHC1_DATA4
|-
|ALT1ALT5|SAI6_MCLKGPIO2_IO06|-| rowspan="3" |J1.148(eMMC on board)| rowspan="3" |NAND_DATA04| rowspan="3" |CPU.NAND_DATA04| rowspan="3" |L20| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA04
|-
|ALT2ALT1|SAI1_TX_SYNCQSPI_B_DATA0
|-
|ALT3ALT5|SAI1_TX_DATA4GPIO3_IO10
|-
|ALT4rowspan="2" |J1.150(NAND on board)| rowspan="2" |SD1_DATA5| rowspan="2" |CPU.SD1_DATA5| rowspan="2" |P24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|CORESIGHT_TRACE7USDHC1_DATA5
|-
|ALT5
|GPIO4_IO09GPIO2_IO07
|-
|ALT6|SRC_BOOT_CFG7|-| rowspan="63" |J4J1.3150(eMMC on board)| rowspan="63" |SAI1_RXD6NAND_DATA05| rowspan="63" |CPU.SAI1_RXD6NAND_DATA05| rowspan="63" |G2J22| rowspan="63" |NVCC_3V3| rowspan="63" |I/O| rowspan="63" |internally used for BOOT config
|ALT0
|SAI1_RX_DATA6RAWNAND_DATA05
|-
|ALT1
|SAI6_TX_SYNCQSPI_B_DATA1
|-
|ALT2ALT5|SAI6_RX_SYNCGPIO3_IO11
|-
|ALT4rowspan="2" |J1.152(NAND on board)| rowspan="2" |SD1_DATA6| rowspan="2" |CPU.SD1_DATA6| rowspan="2" |R25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|CORESIGHT_TRACE6USDHC1_DATA6
|-
|ALT5
|GPIO4_IO08GPIO2_IO08
|-
|ALT6|SRC_BOOT_CFG6|-| rowspan="73" |J4J1.4152(eMMC on board)| rowspan="73" |SAI1_RXD5NAND_DATA06| rowspan="73" |CPU.SAI1_RXD5NAND_DATA06| rowspan="73" |F1L19| rowspan="73" |NVCC_3V3| rowspan="73" |I/O| rowspan="73" |internally used for BOOT config
|ALT0
|SAI1_RX_DATA5RAWNAND_DATA06
|-
|ALT1
|SAI6_TX_DATA0QSPI_B_DATA2
|-
|ALT2ALT5|SAI6_RX_DATA0GPIO3_IO12
|-
|ALT3rowspan="2" |J1.154(NAND on board)|SAI1_RX_SYNCrowspan="2" |SD1_DATA7|-rowspan="2" |CPU.SD1_DATA7| rowspan="2" |T25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT4ALT0|CORESIGHT_TRACE5USDHC1_DATA7
|-
|ALT5
|GPIO4_IO07GPIO2_IO09
|-
|ALT6|SRC_BOOT_CFG5|-| rowspan="63" |J4J1.5154(eMMC on board)| rowspan="63" |SAI1_RXD4NAND_DATA07| rowspan="63" |CPU.SAI1_RXD4NAND_DATA07| rowspan="63" |J1M19| rowspan="63" |NVCC_3V3| rowspan="63" |I/O| rowspan="63" |internally used for BOOT config|ALT0|SAI1_RX_DATA4RAWNAND_DATA07
|-
|ALT1
|SAI6_TX_BCLK|-|ALT2|SAI6_RX_BCLK|-|ALT4|CORESIGHT_TRACE4QSPI_B_DATA3
|-
|ALT5
|GPIO4_IO06GPIO3_IO13
|-
|ALT6J1.156(NAND on board)|NAND_RE_B|CPU.NAND_RE_B|K19|NVCC_3V3|I/O|Internally used for NAND, do not connect||SRC_BOOT_CFG4
|-
| rowspan="53" |J4J1.6156(eMMC on board)| rowspan="53" |SAI1_RXD3NAND_RE_B| rowspan="53" |CPU.SAI1_RXD3NAND_RE_B| rowspan="53" |J2K19| rowspan="53" |NVCC_3V3| rowspan="53" |I/O| rowspan="53" |internally used for BOOT config
|ALT0
|SAI1_RX_DATA3RAWNAND_RE_B
|-
|ALT1
|SAI5_RX_DATA3|-|ALT4|CORESIGHT_TRACE3QSPI_B_DQS
|-
|ALT5
|GPIO4_IO05GPIO3_IO15
|-
|ALT6J1.158(NAND on board)|NAND_READY_B|CPU.NAND_READY_B|K20|NVCC_3V3|I/O|Internally used for NAND, do not connect||SRC_BOOT_CFG3
|-
| rowspan="52" |J4J1.7158(eMMC on board)| rowspan="52" |SAI1_RXD2NAND_READY_B| rowspan="52" |CPU.SAI1_RXD2NAND_READY_B| rowspan="52" |H2K20| rowspan="52" |NVCC_3V3| rowspan="52" |I/O| rowspan="52" |internally used for BOOT config
|ALT0
|SAI1_RX_DATA2|-|ALT1|SAI5_RX_DATA2|-|ALT4|CORESIGHT_TRACE2RAWNAND_READY_B
|-
|ALT5
|GPIO4_IO04GPIO3_IO16
|-
|ALT6J1.160(NAND on board)|NAND_WE_B|CPU.NAND_WE_B|K22|NVCC_3V3|I/O|Internally used for NAND, do not connect||SRC_BOOT_CFG2
|-
| rowspan="52" |J4J1.8160(eMMC on board)| rowspan="52" |SAI1_RXD1NAND_WE_B| rowspan="52" |CPU.SAI1_RXD1NAND_WE_B| rowspan="52" |L2K22| rowspan="52" |NVCC_3V3| rowspan="52" |I/O| rowspan="52" |internally used for BOOT config
|ALT0
|SAI1_RX_DATA1|-|ALT1|SAI5_RX_DATA1|-|ALT4|CORESIGHT_TRACE1RAWNAND_WE_B
|-
|ALT5
|GPIO4_IO03GPIO3_IO17
|-
|ALT6J1.162(NAND on board)|NAND_WP_B|CPU.NAND_WP_B|K21|NVCC_3V3|I/O|Internally used for NAND, do not connect||SRC_BOOT_CFG1
|-
| rowspan="52" |J4J1.9162(eMMC on board)| rowspan="52" |SAI1_RXD0NAND_WP_B| rowspan="52" |CPU.SAI1_RXD0NAND_WP_B| rowspan="52" |K2K21| rowspan="52" |NVCC_3V3| rowspan="52" |I/O| rowspan="52" |internally used for BOOT config
|ALT0
|SAI1_RX_DATA0|-|ALT1|SAI5_RX_DATA0|-|ALT4|CORESIGHT_TRACE0RAWNAND_WP_B
|-
|ALT5
|GPIO4_IO02GPIO3_IO18
|-
|ALT6J1.164|DGND|DGND| -|<nowiki>-</nowiki>|G|||SRC_BOOT_CFG0
|-
| rowspan="4" |J4J1.10166| rowspan="4" |SAI1_RXCCLK1_N| rowspan="4" |CPU.SAI1_RXCCLK1_N| rowspan="4" |K1T23| rowspan="4" |NVCC_3V3| rowspan="4" |I/OD| rowspan="4" ||ALT0|SAI1_RX_BCLK
|-
|ALT1J1.168|CLK1_P|CPU.CLK1_P|R23||D|||SAI5_RX_BCLK
|-
|ALT4J1.170|USB2_RXN|CPU.USB2_RX_N|B8||D|||CORESIGHT_TRACE_CTL
|-
|ALT5|GPIO4_IO01|-| rowspan="4" |J4J1.11172| rowspan="4" |SAI1_RXFSUSB2_RXP| rowspan="4" |CPU.SAI1_RXFSUSB2_RX_P| rowspan="4" |L1A8| rowspan="4" |NVCC_3V3| rowspan="4" |I/OD| rowspan="4" ||ALT0|SAI1_RX_SYNC
|-
|ALT1J1.174|USB2_TXN|CPU.USB2_TX_N|B9||D|||SAI5_RX_SYNC
|-
|ALT4J1.176|USB2_TXP|CPU.USB2_TX_P|A9||D|||CORESIGHT_TRACE_CLK
|-
|ALT5J1.178|USB1_RXN|CPU.USB1_RX_N|B12||D|||GPIO4_IO00
|-
|J4J1.12180|DGNDUSB1_RXP|CPU.USB1_RX_P|A12|DGND| -D|<nowiki>-</nowiki>|G
|
| colspan="2" |
|-
| rowspan="4" |J4J1.13182| rowspan="4" |SAI1_MCLKUSB1_TXN| rowspan="4" |CPU.SAI1_MCLKUSB1_TX_N| rowspan="4" |B13| rowspan="4" |NVCC_3V3| rowspan="4" |I/OD| rowspan="4" ||ALT0|SAI1_MCLK
|-
|ALT1J1.184|USB1_TXP|CPU.USB1_TX_P|A13||D|||SAI5_MCLK
|-
|ALT2J1.186|USB1_VBUS|CPU.USB1_VBUS|D14| -|S|Absolute maximum ratings 5.25V||SAI1_TX_BCLK
|-
|ALT5J1.188|USB2_VBUS|CPU.USB2_VBUS|D9| -|S|Absolute maximum ratings 5.25V||GPIO4_IO20
|-
|J4J1.14190
|DGND
|DGND
|G
|
| colspan="2" |
|-
| rowspan="4" |J4J1.15192| rowspan="4" |SAI1_TXFSUSB1_ID| rowspan="4" |CPU.SAI1_TXFSUSB1_ID| rowspan="4" |H4C14| rowspan="4" |NVCC_3V3VDD_PHY_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI1_TX_SYNC
|-
|ALT1J1.194|USB2_ID|CPU.USB2_ID|C9|VDD_PHY_3V3|I|||SAI5_TX_SYNC
|-
|ALT4J1.196|CORESIGHT_EVENTOUSB1_DN|CPU.USB1_DN|B14|-|ALT5D|||GPIO4_IO10
|-
| rowspan="4" |J4J1.16198| rowspan="4" |SAI1_TXCUSB1_DP| rowspan="4" |CPU.SAI1_TXCUSB1_DP| rowspan="4" |J5A14| rowspan="4" |NVCC_3V3-| rowspan="4" |I/OD| rowspan="4" ||ALT0|SAI1_TX_BCLK
|-
|ALT1J1.200|USB2_DP|CPU.USB2_DP|A10| -|D|||SAI5_TX_BCLK
|-
|ALT4J1.202|USB2_DN|CPU.USB2_DN|B10| -|D|||CORESIGHT_EVENTI
|-
|ALT5J1.204|DGND|DGND| -|<nowiki>-</nowiki>|G|||GPIO4_IO11
|-
| rowspan} =="5" |ONE PIECE J4.17pins declaration =={| rowspanclass="5wikitable" |SAI1_TXD0| rowspan! latexfontsize="5scriptsize" |CPU.SAI1_TXD0Pin | rowspan! latexfontsize="5scriptsize" |F2Pin Name| rowspan! latexfontsize="5scriptsize" |NVCC_3V3Internal Connections | rowspan! latexfontsize="5scriptsize" |IBall/Opin # ! latexfontsize="scriptsize" | rowspanVoltage domain! latexfontsize="5scriptsize" |internally used for BOOT configType ! latexfontsize="scriptsize" |ALT0Notes! colspan="2" |SAI1_TX_DATA0Alternative Functions
|-
|J4.1|DGND|DGND| -|<nowiki>-</nowiki>|G||||-| rowspan="7" |J4.2| rowspan="7" |SAI1_RXD7| rowspan="7" |CPU.SAI1_RXD7| rowspan="7" |G1| rowspan="7" |NVCC_3V3| rowspan="7" |I/O| rowspan="7" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_RX_DATA7|-|ALT1|SAI5_TX_DATA0SAI6_MCLK|-|ALT2|SAI1_TX_SYNC|-|ALT3|SAI1_TX_DATA4
|-
|ALT4
|CORESIGHT_TRACE8CORESIGHT_TRACE7
|-
|ALT5
|GPIO4_IO12GPIO4_IO09
|-
|ALT6
|SRC_BOOT_CFG8SRC_BOOT_CFG7
|-
| rowspan="56" |J4.183| rowspan="56" |SAI1_TXD1SAI1_RXD6| rowspan="56" |CPU.SAI1_TXD1SAI1_RXD6| rowspan="56" |E2G2| rowspan="56" |NVCC_3V3| rowspan="56" |I/O| rowspan="56" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA1SAI1_RX_DATA6
|-
|ALT1
|SAI5_TX_DATA1SAI6_TX_SYNC|-|ALT2|SAI6_RX_SYNC
|-
|ALT4
|CORESIGHT_TRACE9CORESIGHT_TRACE6
|-
|ALT5
|GPIO4_IO13GPIO4_IO08
|-
|ALT6
|SRC_BOOT_CFG9SRC_BOOT_CFG6
|-
| rowspan="57" |J4.194| rowspan="57" |SAI1_TXD2SAI1_RXD5| rowspan="57" |CPU.SAI1_TXD2SAI1_RXD5| rowspan="57" |B2F1| rowspan="57" |NVCC_3V3| rowspan="57" |I/O| rowspan="57" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA2SAI1_RX_DATA5
|-
|ALT1
|SAI5_TX_DATA2SAI6_TX_DATA0
|-
|ALT2|SAI6_RX_DATA0|-|ALT3|SAI1_RX_SYNC|-|ALT4|CORESIGHT_TRACE10CORESIGHT_TRACE5
|-
|ALT5
|GPIO4_IO14GPIO4_IO07
|-
|ALT6
|SRC_BOOT_CFG10SRC_BOOT_CFG5
|-
| rowspan="56" |J4.205| rowspan="56" |SAI1_TXD3SAI1_RXD4| rowspan="56" |CPU.SAI1_TXD3SAI1_RXD4| rowspan="56" |D1J1| rowspan="56" |NVCC_3V3| rowspan="56" |I/O| rowspan="56" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA3SAI1_RX_DATA4
|-
|ALT1
|SAI5_TX_DATA3SAI6_TX_BCLK|-|ALT2|SAI6_RX_BCLK
|-
|ALT4
|CORESIGHT_TRACE11CORESIGHT_TRACE4
|-
|ALT5
|GPIO4_IO15GPIO4_IO06
|-
|ALT6
|SRC_BOOT_CFG11SRC_BOOT_CFG4
|-
| rowspan="65" |J4.216| rowspan="65" |SAI1_TXD4SAI1_RXD3| rowspan="65" |CPU.SAI1_TXD4SAI1_RXD3| rowspan="65" |D2J2| rowspan="65" |NVCC_3V3| rowspan="65" |I/O| rowspan="65" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA4SAI1_RX_DATA3
|-
|ALT1
|SAI6_RX_BCLK|-|ALT2|SAI6_TX_BCLKSAI5_RX_DATA3
|-
|ALT4
|CORESIGHT_TRACE12CORESIGHT_TRACE3
|-
|ALT5
|GPIO4_IO16GPIO4_IO05
|-
|ALT6
|SRC_BOOT_CFG12SRC_BOOT_CFG3
|-
| rowspan="65" |J4.227| rowspan="65" |SAI1_TXD5SAI1_RXD2| rowspan="65" |CPU.SAI1_TXD5SAI1_RXD2| rowspan="65" |C2H2| rowspan="65" |NVCC_3V3| rowspan="65" |I/O| rowspan="65" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA5SAI1_RX_DATA2
|-
|ALT1
|SAI6_RX_DATA0|-|ALT2|SAI6_TX_DATA0SAI5_RX_DATA2
|-
|ALT4
|CORESIGHT_TRACE13CORESIGHT_TRACE2
|-
|ALT5
|GPIO4_IO17GPIO4_IO04
|-
|ALT6
|SRC_BOOT_CFG13SRC_BOOT_CFG2
|-
| rowspan="65" |J4.238| rowspan="65" |SAI1_TXD6SAI1_RXD1| rowspan="65" |CPU.SAI1_TXD6SAI1_RXD1| rowspan="65" |B3L2| rowspan="65" |NVCC_3V3| rowspan="65" |I/O| rowspan="65" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA6SAI1_RX_DATA1
|-
|ALT1
|SAI6_RX_SYNC|-|ALT2|SAI6_TX_SYNCSAI5_RX_DATA1
|-
|ALT4
|CORESIGHT_TRACE14CORESIGHT_TRACE1
|-
|ALT5
|GPIO4_IO18GPIO4_IO03
|-
|ALT6
|SRC_BOOT_CFG14SRC_BOOT_CFG1
|-
| rowspan="5" |J4.249| rowspan="5" |SAI1_TXD7SAI1_RXD0| rowspan="5" |CPU.SAI1_TXD7SAI1_RXD0| rowspan="5" |C1K2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |internally Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA7SAI1_RX_DATA0
|-
|ALT1
|SAI6_MCLKSAI5_RX_DATA0
|-
|ALT4
|CORESIGHT_TRACE15CORESIGHT_TRACE0
|-
|ALT5
|GPIO4_IO19GPIO4_IO02
|-
|ALT6
|SRC_BOOT_CFG15SRC_BOOT_CFG0|-| rowspan="4" |J4.10| rowspan="4" |SAI1_RXC| rowspan="4" |CPU.SAI1_RXC| rowspan="4" |K1| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI1_RX_BCLK
|-
|J4.25ALT1|SAI5_RX_BCLK|-|DGNDALT4|DGNDCORESIGHT_TRACE_CTL| -|<nowiki>-</nowiki>ALT5|GGPIO4_IO01|-| colspanrowspan="24" |J4.11|}===Pinout Table J5 pins declaration ==={| classrowspan="wikitable4" |SAI1_RXFS! latexfontsize| rowspan="scriptsize4" | Pin CPU.SAI1_RXFS! latexfontsize| rowspan="scriptsize4" | Pin NameL1! latexfontsize| rowspan="scriptsize4" | Internal Connections NVCC_3V3! latexfontsize| rowspan="scriptsize4" | BallI/pin # O! latexfontsize| rowspan="scriptsize4" |<nowiki> Voltage|ALT0|SAI1_RX_SYNC|-|ALT1|SAI5_RX_SYNC|-|ALT4|domain</nowiki>CORESIGHT_TRACE_CLK! latexfontsize="scriptsize" | Type -! latexfontsize="scriptsize" | NotesALT5! latexfontsize="scriptsize" | Alternative FunctionsGPIO4_IO00
|-
|J5J4.112
|DGND
|DGND
|<nowiki>-</nowiki>
|G
| colspan="2" ||
|-
|J5rowspan="4" |J4.213|PCIE2_RXNrowspan="4" |SAI1_MCLK| rowspan="4" |CPU.PCIE2_RXN_NSAI1_MCLK|D24rowspan="4" || -rowspan="4" |NVCC_3V3|Drowspan="4" |I/O| colspanrowspan="24" ||ALT0|SAI1_MCLK|-|ALT1|SAI5_MCLK |-|ALT2|SAI1_TX_BCLK
|-
|J5.3ALT5|PCIE2_RXP|CPU.PCIE2_RXN_P|D25| -|D| colspan="2" |GPIO4_IO20
|-
|J5J4.414
|DGND
|DGND
|<nowiki>-</nowiki>
|G
| colspan="2" ||
|-
|J5rowspan="4" |J4.515|PCIE2_TXNrowspan="4" |SAI1_TXFS| rowspan="4" |CPU.PCIE2_TXN_NSAI1_TXFS|E24rowspan="4" |H4| -rowspan="4" |NVCC_3V3|Drowspan="4" |I/O| colspanrowspan="24" ||ALT0|SAI1_TX_SYNC
|-
|J5.6ALT1|PCIE2_TXP|CPU.PCIE2_TXN_P|E25| -|D| colspan="2" |SAI5_TX_SYNC
|-
|J5.7ALT4|DGND|DGND| -|<nowiki>-</nowiki>|G| colspan="2" |CORESIGHT_EVENTO
|-
|J5.8ALT5|PCIE2_REF_CLKN|CPU.PCIE2_REF_PAD_CLK_N|F24| -|D| colspan="2" |GPIO4_IO10
|-
|J5rowspan="4" |J4.916|PCIE2_REF_CLKProwspan="4" |SAI1_TXC| rowspan="4" |CPU.PCIE2_REF_PAD_CLK_PSAI1_TXC|F25rowspan="4" |J5| -rowspan="4" |NVCC_3V3|Drowspan="4" |I/O| colspanrowspan="24" ||ALT0|SAI1_TX_BCLK
|-
|J5.10ALT1|DGND|DGND| -|<nowiki>-</nowiki>|G| colspan="2" |SAI5_TX_BCLK
|-
|J5.11ALT4|CSI_P2_CKN|CPU.MIPI_CSI2_CLK_N|A19| -|D| colspan="2" |CORESIGHT_EVENTI
|-
|J5.12ALT5|CSI_P2_CKP|CPU.MIPI_CSI2_CLK_P|B19| -|D| colspan="2" |GPIO4_IO11
|-
|J5rowspan="5" |J4.1317|DGNDrowspan="5" |SAI1_TXD0|DGNDrowspan="5" |CPU.SAI1_TXD0| -rowspan="5" |F2|<nowiki>-</nowiki>rowspan="5" |NVCC_3V3|Growspan="5" |I/O| colspanrowspan="25" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_TX_DATA0|-|ALT1|SAI5_TX_DATA0
|-
|J5.14ALT4|CSI_P2_DN0|CPU.MIPI_CSI2_D0_N|C20| -|D| colspan="2" |CORESIGHT_TRACE8
|-
|J5.15ALT5|CSI_P2_DP0|CPU.MIPI_CSI2_D0_P|D10| -|D| colspan="2" |GPIO4_IO12
|-
|J5.16ALT6|CSI_P2_DN1|CPU.MIPI_CSI2_D1_N|A20| -|D| colspan="2" |SRC_BOOT_CFG8
|-
|J5rowspan="5" |J4.1718|CSI_P2_DP1rowspan="5" |SAI1_TXD1| rowspan="5" |CPU.MIPI_CSI2_D1_PSAI1_TXD1|B20rowspan="5" |E2| -rowspan="5" |NVCC_3V3|Drowspan="5" |I/O| colspanrowspan="25" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_TX_DATA1
|-
|J5.18ALT1|DGND|DGND| -|<nowiki>-</nowiki>|G| colspan="2" |SAI5_TX_DATA1
|-
|J5.19ALT4|CSI_P2_DN2|CPU.MIPI_CSI2_D2_N|A21| -|D| colspan="2" |CORESIGHT_TRACE9
|-
|J5.20ALT5|CSI_P2_DP2|CPU.MIPI_CSI2_D2_P|B21| -|D| colspan="2" |GPIO4_IO13
|-
|J5.21ALT6|CSI_P2_DN3|CPU.MIPI_CSI2_D3_N|C19| -|D| colspan="2" |SRC_BOOT_CFG9
|-
|J5.22|CSI_P2_DP3|CPU.MIPI_CSI2_D3_P|D19| -|D| colspanrowspan="25" ||-|J5J4.2319|DGND|DGND| -|<nowiki>-</nowiki>|G| colspanrowspan="25" ||-SAI1_TXD2| rowspan="45" |J5CPU.24SAI1_TXD2| rowspan="45" |I2C4_SCLB2| rowspan="45" |CPU.I2C4_SCLNVCC_3V3| rowspan="45" |F8I/O| rowspan="45" |NVCC_3V3Internally used for BOOT config| rowspan="4" |I/OCould be pulled-up or down during bootstrap.
|ALT0
|I2C4_SCLSAI1_TX_DATA2
|-
|ALT1
|PWM2_OUTSAI5_TX_DATA2
|-
|ALT2ALT4|PCIE1_CLKREQ_BCORESIGHT_TRACE10
|-
|ALT5
|GPIO5_IO20GPIO4_IO14|-|ALT6|SRC_BOOT_CFG10
|-
| rowspan="45" |J5J4.2520| rowspan="45" |I2C4_SDASAI1_TXD3| rowspan="45" |CPU.I2C4_SDASAI1_TXD3| rowspan="45" |F9D1| rowspan="45" |NVCC_3V3| rowspan="45" |I/O| rowspan="5" |Internally used for BOOT configCould be pulled-up or down during bootstrap.
|ALT0
|I2C4_SDASAI1_TX_DATA3
|-
|ALT1
|PWM1_OUTSAI5_TX_DATA3
|-
|ALT2ALT4|PCIE2_CLKREQ_BCORESIGHT_TRACE11
|-
|ALT5
|GPIO5_IO21|} ===Pinout Table JD5 pins declaration ==={| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! latexfontsize="scriptsize" | Alternative FunctionsGPIO4_IO15
|-
|JD5ALT6|SRC_BOOT_CFG11|-| rowspan="6" |J4.121| rowspan="6" |SAI1_TXD4|DGNDrowspan="6" |CPU.SAI1_TXD4|DGNDrowspan="6" |D2| -rowspan="6" |NVCC_3V3|<nowiki>-<rowspan="6" |I/nowiki>O|Growspan="6" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_TX_DATA4
|-
|JD5.2|EEPROM_WP|Internal EEPROM Write Protect| -|NVCC_3V3|I|ALT1|SAI6_RX_BCLK
|-
|JD5.3|NC|Not Connected| -| -|Z|ALT2|SAI6_TX_BCLK
|-
|JD5.4|JTAG_TCK|CPU.JTAG_TCK|T5|NVCC_3V3|I|internal pull-up 10k to NVCC_3V3ALT4|CORESIGHT_TRACE12
|-
|JD5.5ALT5|JTAG_TMSGPIO4_IO16|CPU.JTAG_TMS|V5|NVCC_3V3|I-|ALT6|SRC_BOOT_CFG12
|-
|JD5rowspan="6" |J4.22| rowspan="6" |SAI1_TXD5|JTAG_TDOrowspan="6" |CPU.JTAG_TDOSAI1_TXD5|U5rowspan="6" |C2| rowspan="6" |NVCC_3V3|rowspan="6" |I/O|rowspan="6" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_TX_DATA5
|-
|JD5.7|JTAG_TDI|CPU.JTAG_TDI|W5|NVCC_3V3|I|ALT1|SAI6_RX_DATA0
|-
|JD5.8|JTAG_nTRST|CPU.JTAG_TRST_B|U6|NVCC_3V3|I|ALT2|SAI6_TX_DATA0
|-
|JD5ALT4|CORESIGHT_TRACE13|-|ALT5|GPIO4_IO17|-|ALT6|SRC_BOOT_CFG13|-| rowspan="6" |J4.923|CPU_PORnrowspan="6" |SAI1_TXD6| rowspan="6" |CPU.POR_BSAI1_TXD6PMIC.RESETMCU| rowspan="6" |B3|W203rowspan="6" |NVCC_3V3|NVCC_SNVSrowspan="6" |I/O|internal pullrowspan="6" |Internally used for BOOT configCould be pulled-up 100k to NVCC_SNVSor down during bootstrap.|ALT0|SAI1_TX_DATA6|-|ALT1|SAI6_RX_SYNC|-|ALT2|SAI6_TX_SYNC|-|ALT4|CORESIGHT_TRACE14|-|ALT5|GPIO4_IO18|-|ALT6|SRC_BOOT_CFG14
|-
|JD5rowspan="5" |J4.24| rowspan="5" |SAI1_TXD7| rowspan="5" |CPU.10SAI1_TXD7| rowspan="5" |C1| rowspan="5" |NVCC_3V3|NVCC_3V3rowspan="5" |I/O| rowspan="5" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_TX_DATA7|-|ALT1|SAI6_MCLK|-|ALT4|CORESIGHT_TRACE15|-|ALT5|GPIO4_IO19|-|ALT6|SRC_BOOT_CFG15|-|J4.25|DGND|DGND| -
|<nowiki>-</nowiki>
|SG|
|
|
|}
 
==ONE PIECE J5 pins declaration ==
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" | Voltage domain
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
! colspan="2" |Alternative Functions
|-
|J5.1
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.2
|PCIE2_RXN
|CPU.PCIE2_RXN_N
|D24
| -
|D
|
|
|
|-
|J5.3
|PCIE2_RXP
|CPU.PCIE2_RXN_P
|D25
| -
|D
|
|
|
|-
|J5.4
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.5
|PCIE2_TXN
|CPU.PCIE2_TXN_N
|E24
| -
|D
|
|
|
|-
|J5.6
|PCIE2_TXP
|CPU.PCIE2_TXN_P
|E25
| -
|D
|
|
|
|-
|J5.7
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.8
|PCIE2_REF_CLKN
|CPU.PCIE2_REF_PAD_CLK_N
|F24
| -
|D
|
|
|
|-
|J5.9
|PCIE2_REF_CLKP
|CPU.PCIE2_REF_PAD_CLK_P
|F25
| -
|D
|
|
|
|-
|J5.10
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.11
|CSI_P2_CKN
|CPU.MIPI_CSI2_CLK_N
|A19
| -
|D
|
|
|
|-
|J5.12
|CSI_P2_CKP
|CPU.MIPI_CSI2_CLK_P
|B19
| -
|D
|
|
|
|-
|J5.13
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.14
|CSI_P2_DN0
|CPU.MIPI_CSI2_D0_N
|C20
| -
|D
|
|
|
|-
|J5.15
|CSI_P2_DP0
|CPU.MIPI_CSI2_D0_P
|D10
| -
|D
|
|
|
|-
|J5.16
|CSI_P2_DN1
|CPU.MIPI_CSI2_D1_N
|A20
| -
|D
|
|
|
|-
|J5.17
|CSI_P2_DP1
|CPU.MIPI_CSI2_D1_P
|B20
| -
|D
|
|
|
|-
|J5.18
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.19
|CSI_P2_DN2
|CPU.MIPI_CSI2_D2_N
|A21
| -
|D
|
|
|
|-
|J5.20
|CSI_P2_DP2
|CPU.MIPI_CSI2_D2_P
|B21
| -
|D
|
|
|
|-
|J5.21
|CSI_P2_DN3
|CPU.MIPI_CSI2_D3_N
|C19
| -
|D
|
|
|
|-
|J5.22
|CSI_P2_DP3
|CPU.MIPI_CSI2_D3_P
|D19
| -
|D
|
|
|
|-
|J5.23
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
| rowspan="4" |J5.24
| rowspan="4" |I2C4_SCL
| rowspan="4" |CPU.I2C4_SCL
| rowspan="4" |F8
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|I2C4_SCL
|-
|ALT1
|PWM2_OUT
|-
|ALT2
|PCIE1_CLKREQ_B
|-
|ALT5
|GPIO5_IO20
|-
| rowspan="4" |J5.25
| rowspan="4" |I2C4_SDA
| rowspan="4" |CPU.I2C4_SDA
| rowspan="4" |F9
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|I2C4_SDA
|-
|ALT1
|PWM1_OUT
|-
|ALT2
|PCIE2_CLKREQ_B
|-
|ALT5
|GPIO5_IO21
|}
U0007
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