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MITO 8M SOM/MITO 8M Hardware/Pinout Table

8,576 bytes added, 17:49, 28 December 2023
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<section begin="History" />
{| style="border-collapse:collapse; "
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
|-
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0{{oldid| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" 10368|Sep 2020/09/29}}
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |2021/02/02
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |Add pull-up/down information
|-
|}
<section end="History" /><section begin="Body" />==Connectors and Pinout Table=====Introduction=description==
This chapter contains the pinout === Connectors description of ===In the following table are described all available connectors integrated on MITO 8M module, grouped in two tables (odd and even pins) that report the SOM:{| class="wikitable"|-!Connector name!Connector Type!Notes!Carrier board counterpart|-|J1|SODIMM edge connector 204 pin mapping of the 204|partially compatible with [[AXEL Lite SOM]]|TE Connectivity 2-2013289-1|-|J4|ONE PIECE connector single row 25pins||SAMTEC FSI-125-03-G-S-AD-TR|-|J5|ONE PIECE connector single row 25pins||SAMTEC FSI-125-03-G-S-pin SOAD-DIMM TR|}The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to MITO 8M connectorpinout specifications.See the images below for reference:
[[File:MITO 8M-conn-TOP.png|500px|thumb|MITO 8M TOP view|none]]
[[File:MITO 8M-conn-BOTTOM.png|500px|thumb|MITO 8M BOTTOM view|none]]
 
Below a detailed description of the pinout, grouped in the following tables:
* two tables (ODD and EVEN pins) that report the pin mapping of the 204-pin SO-DIMM edge
* a dedicated tables for J4 one-piece connector
* a dedicated tables for J5 one-piece connector
 
=== Pinout Table description ===
Each row in the pinout tables contains the following information:
 {| class="wikitable" style="width:50%;"
|-
|'''Pin'''
|-
|'''Pin Name'''
| Pin (signal) name on the AxelLite MITO 8M connectors
|-
|'''Internal<br>connections'''
| Connections to the Axel Ultra components
* CPU.<x> : pin connected to CPU pad named <x>
* PMIC.<x> : pin connected to the Power Manager IC(NXP PF4210)* LAN.<x> : pin connected to the LAN PHY(MICROCHIP KSZ9031RNX)* BRIDGE.<x> : pin connected to the MIPI-to-LVDS bridge* SV.<x>: pin connected to voltage supervisor(TI SN65DSI84)
|-
|'''Ball/pin #'''
|}
===Pinout Table SODIMM J1 ODD pins declaration ===
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| colspan="2" |
|-
|J1.3
|S
|
| colspan="2" |
|-
|J1.5
|S
|
| colspan="2" |
|-
|J1.7
|S
|
| colspan="2" |
|-
|J1.9
|S
|
| colspan="2" |
|-
|J1.11
|G
|
| colspan="2" |
|-
|J1.13
|NVCC_1V8
|I/O
|must Must be level translated if used @ 3V3Internally pulled-up to 1.8V during bootstrap| colspan="2" |
|-
|J1.15
|NVCC_1V8
|I/O
|must Must be level translated if used @ 3V3Internally pulled-up to 1.8V during bootstrap| colspan="2" |
|-
|J1.17
|G
|
| colspan="2" |
|-
|J1.19
|D
|
| colspan="2" |
|-
|J1.21
|D
|
| colspan="2" |
|-
|J1.23
|D
|
| colspan="2" |
|-
|J1.25
|D
|
| colspan="2" |
|-
|J1.27
|D
|
| colspan="2" |
|-
|J1.29
|D
|
| colspan="2" |
|-
|J1.31
|D
|
| colspan="2" |
|-
|J1.33
|D
|
| colspan="2" |
|-
|J1.35
|G
|
| colspan="2" |
|-
| rowspan="4" |J1.37
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for ETH PHY reset, do not connect
|ALT0
|GPIO1_IO01
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |Internally used, do not connect
|ALT0
|GPIO1_IO13
|
|
| colspan="2" |
|-
| rowspan="3" |J1.47
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| colspan="2" |
|-
| rowspan="3" |J1.59
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |Internally used for MIPI-to-LVDS interrupt, do not connectPulled-up to NVCC_3V3
|ALT0
|GPIO1_IO05
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for MIPI-to-LVDS enable, do not connect
|ALT0
|GPIO1_IO06
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| colspan="2" |
|-
| rowspan="2" |J1.75
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| colspan="2" |
|-
| rowspan="3" |J1.89
|I/O
|
| colspan="2" |
|-
|J1.103
|I/O
|
| colspan="2" |
|-
|J1.105
|D
|connected with capacitor in series
| colspan="2" |
|-
|J1.107
|D
|connected with capacitor in series
| colspan="2" |
|-
|J1.109
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| colspan="2" |
|-
|J1.111
|D
|connected with capacitor in series
| colspan="2" |
|-
|J1.113
|D
|connected with capacitor in series
| colspan="2" |
|-
|J1.115
|D
|connected with capacitor in series
| colspan="2" |
|-
|J1.117
|D
|connected with capacitor in series
| colspan="2" |
|-
|J1.119
|D
|connected with capacitor in series
| colspan="2" |
|-
|J1.121
|D
|connected with capacitor in series
| colspan="2" |
|-
|J1.123
|D
|connected with capacitor in series
| colspan="2" |
|-
|J1.125
|D
|connected with capacitor in series
| colspan="2" |
|-
|J1.127
|I/O
|
| colspan="2" |
|-
|J1.129
|I/O
|
| colspan="2" |
|-
|J1.131
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| colspan="2" |
|-
|J1.133
|D
|
| colspan="2" |
|-
|J1.135
|D
|
| colspan="2" |
|-
|J1.137
|D
|
| colspan="2" |
|-
|J1.139
|D
|
| colspan="2" |
|-
|J1.141
|D
|
| colspan="2" |
|-
|J1.143
|D
|
| colspan="2" |
|-
|J1.145
|D
|
| colspan="2" |
|-
|J1.147
|D
|
| colspan="2" |
|-
|J1.149
|D
|
| colspan="2" |
|-
|J1.151
|D
|
| colspan="2" |
|-
|J1.153
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| colspan="2" |
|-
|J1.155
|D
|
| colspan="2" |
|-
|J1.157
|D
|
| colspan="2" |
|-
|J1.159
|D
|
| colspan="2" |
|-
|J1.161
|D
|
| colspan="2" |
|-
|J1.163
|D
|
| colspan="2" |
|-
|J1.165
|D
|
| colspan="2" |
|-
|J1.167
|D
|
| colspan="2" |
|-
|J1.169
|D
|
| colspan="2" |
|-
|J1.171
|D
|
| colspan="2" |
|-
|J1.173
|D
|
| colspan="2" |
|-
|J1.175
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| colspan="2" |
|-
| rowspan="2" |J1.177
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="63" |used as default Linux console
|ALT0
|UART2_TX
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |used as default Linux console
|ALT0
|UART2_RXD
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| colspan="2" |
|-
|}
===Pinout Table SODIMM J1 EVEN pins declaration ===
{| class="wikitable"
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
|G
|
| colspan="2" |
|-
|J1.4
|S
|
| colspan="2" |
|-
|J1.6
|S
|
| colspan="2" |
|-
|J1.8
|S
|
| colspan="2" |
|-
|J1.10
|S
|
| colspan="2" |
|-
|J1.12
|G
|
| colspan="2" |
|-
|J1.14
|S
|
| colspan="2" |
|-
|J1.16
|I
|internal pull-up 100k to NVCC_SNVS
| colspan="2" |
|-
|J1.18
|O
|
| colspan="2" |
|-
|J1.20
|I
|internal pull-up to NVCC_3V3
| colspan="2" |
|-
|J1.22
|I/O
|internal pull-up 100k to NVCC_SNVS
| colspan="2" |
|-
|J1.24
|I
|internal pull-up to NVCC_SNVS
| colspan="2" |
|-
| rowspan="4" |J1.26
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for SW reset, do not connect
|ALT0
|GPIO1_IO02
|G
|
| colspan="2" |
|-
| rowspan="4" |J1.32
|-
| rowspan="2" |J1.54
| rowspan="2" |SD1_STROBEGPIO1_IO10| rowspan="2" |CPU.SD1_STROBEGPIO1_IO10| rowspan="2" |T24M7| rowspan="2" |NVCC_1V8(NVCC_3V3 on request)
| rowspan="2" |I/O
| rowspan="2" |internally Internally used for eMMC(available on NAND storage SOM) ???ETH PHY interrupt, do not connect
|ALT0
|USDHC1_STROBE GPIO1_IO10
|-
|ALT5ALT1|GPIO2_IO11USB1_OTG_ID
|-
|J1.56
|G
|
| colspan="2" |
|-
| rowspan="4" |J1.58
|G
|
| colspan="2" |
|-
|J1.84
|VDDA_1V8
|D
|Internally used for PCIe CLK, do not connect
|
|
| colspan="2" |
|-
|J1.86
|VDDA_1V8
|D
|Internally used for PCIe CLK, do not connect
|
|
| colspan="2" |
|-
|J1.88
|D
|
| colspan="2" |
|-
|J1.90
|D
|
| colspan="2" |
|-
|J1.92
|D
|
| colspan="2" |
|-
|J1.94
|D
|
| colspan="2" |
|-
|J1.96
|D
|
| colspan="2" |
|-
|J1.98
|D
|
| colspan="2" |
|-
|J1.100
|G
|
| colspan="2" |
|-
|J1.102
|D
|
| colspan="2" |
|-
|J1.104
|D
|
| colspan="2" |
|-
|J1.106
|D
|
| colspan="2" |
|-
|J1.108
|D
|
| colspan="2" |
|-
|J1.110
|D
|
| colspan="2" |
|-
|J1.112
|D
|
| colspan="2" |
|-
|J1.114
|D
|
| colspan="2" |
|-
|J1.116
|D
|
| colspan="2" |
|-
|J1.118
|D
|
| colspan="2" |
|-
|J1.120
|D
|
| colspan="2" |
|-
|J1.122
|G
|
| colspan="2" ||-|J1.124(NAND on board)|NAND_DQS|CPU.NAND_DQS|M20|NVCC_3V3|I/O|Internally used for NAND, do not connect||
|-
| rowspan="3" |J1.124
(eMMC on board)
| rowspan="3" |NAND_DQS
| rowspan="3" |CPU.NAND_DQS
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |internally used for NAND
|ALT0
|RAWNAND_DQS
|ALT5
|GPIO3_IO14
|-
|J1.126
(NAND on board)
|NAND_ALE
|CPU.NAND_ALE
|G19
|NVCC_3V3
|I/O
|Internally used for NAND, do not connect
|
|
|-
| rowspan="3" |J1.126
(eMMC on board)
| rowspan="3" |NAND_ALE
| rowspan="3" |CPU.NAND_ALE
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |internally used for NAND
|ALT0
|RAWNAND_ALE
|-
|ALT1
|QSPI_A_SCLK
|-
|ALT5
|GPIO3_IO00
|-
| rowspan="2" |J1.128(NAND on board)| rowspan="2" |NAND_CE0_B // SD1_CLK|CPU.NAND_CE0_B // rowspan="2" |CPU.SD1_CLK|H19 // rowspan="2" |L25|rowspan="2" |NVCC_3V3(NVCC_1V8 // NVCC_3V3 ???on request)| rowspan="2" |I/O|???rowspan="2" ||ALT0|USDHC1_CLK|-|ALT5|GPIO2_IO00
|-
|rowspan="3" |J1.128(eMMC on board)|rowspan="3" |NAND_CE0_B|rowspan="3" |CPU.NAND_CE0_B|rowspan="3" |H19|rowspan="3" |NVCC_3V3|rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_CE0_B
|-
|J1.130|NAND_CE1_B // SD1_CMD|CPU.NAND_CE1_B // CPU.SD1_CMD|G21 // L24|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT1|QSPI_A_SS0_B
|-
|J1.132|NAND_CE2_B // SD1_RST_B|CPU.NAND_CE2_B // CPU.SD1_RST_B|F21 // R24|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT5|GPIO3_IO01
|-
| rowspan="2" |J1.134130(NAND on board)| rowspan="2" |NAND_CE3_B // SD1_STROBESD1_CMD| rowspan="2" |CPU.NAND_CE3_B // CPU.SD1_STROBESD1_CMD|H20 // T24rowspan="2" |L24|rowspan="2" |NVCC_3V3(NVCC_1V8 // NVCC_3V3 ???on request)| rowspan="2" |I/O|???rowspan="2" ||ALT0|USDHC1_CMD
|-
|J1.136|NAND_CLE|DGND|H21|NVCC_3V3|I/O||ALT5|GPIO2_IO01
|-
| rowspan="3" |J1.138130(eMMC on board)|NAND_DATA00 // SD1_DATA0rowspan="3" |NAND_CE1_B| rowspan="3" |CPU.NAND_DATA00 // CPU.SD1_DATA0NAND_CE1_B|G20 // M25rowspan="3" |G21|NVCC_1V8 // rowspan="3" |NVCC_3V3 ???| rowspan="3" |I/O|???rowspan="3" ||ALT0|RAWNAND_CE1_B
|-
|J1.140|NAND_DATA01 // SD1_DATA1|CPU.NAND_DATA01 // CPU.SD1_DATA1|J20 // M24|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT1|QSPI_A_SS1_B
|-
|J1.142|NAND_DATA02 // SD1_DATA2|CPU.NAND_DATA02 // CPU.SD1_DATA2|H22 // N25|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT5|GPIO3_IO02
|-
| rowspan="2" |J1.144132(NAND on board)| rowspan="2" |NAND_DATA03 // SD1_DATA3SD1_RST_B| rowspan="2" |CPU.NAND_DATA03 // CPU.SD1_DATA3SD1_RST_B|J21 // P25rowspan="2" |R24|rowspan="2" |NVCC_3V3(NVCC_1V8 // NVCC_3V3 ???on request)| rowspan="2" |I/O|???rowspan="2" ||ALT0|USDHC1_RESET_B
|-
|J1.146|DGND|DGND| -|<nowiki>-</nowiki>|G||ALT5|GPIO2_IO10
|-
| rowspan="3" |J1.148132(eMMC on board)|NAND_DATA04 // SD1_DATA4rowspan="3" |NAND_CE2_B| rowspan="3" |CPU.NAND_DATA04 // CPU.SD1_DATA4NAND_CE2_B|L20 // N24rowspan="3" |F21|NVCC_1V8 // rowspan="3" |NVCC_3V3 ???| rowspan="3" |I/O|???rowspan="3" ||ALT0|RAWNAND_CE2_B
|-
|ALT1|QSPI_B_SS0_B|-|ALT5|GPIO3_IO03|-| rowspan="2" |J1.150134(NAND on board)|NAND_DATA05 // SD1_DATA5rowspan="2" |SD1_STROBE| rowspan="2" |CPU.NAND_DATA05 /SD1_STROBE| rowspan="2" |T24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/ O| rowspan="2" ||ALT0|USDHC1_STROBE|-|ALT5|GPIO2_IO11|-| rowspan="3" |J1.134(eMMC on board)| rowspan="3" |NAND_CE3_B| rowspan="3" |CPU.SD1_DATA5NAND_CE3_B|J22 // P24rowspan="3" |H20|NVCC_1V8 // rowspan="3" |NVCC_3V3 ???| rowspan="3" |I/O|???rowspan="3" ||ALT0|RAWNAND_CE3_B|-|ALT1|QSPI_B_SS1_B
|-
|J1.152|NAND_DATA06 // SD1_DATA6|CPU.NAND_DATA06 // CPU.SD1_DATA6|L19 // R25|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT5|GPIO3_IO034
|-
|J1.154136(NAND on board)|NAND_DATA07 // SD1_DATA7NAND_CLE|CPU.NAND_DATA07 // CPU.SD1_DATA7NAND_CLE|M19 // T25H21|NVCC_1V8 // NVCC_3V3 ???
|I/O
|???Internally used for NAND, do not connect
|
|
|-
| rowspan="3" |J1.156136(eMMC on board)| rowspan="3" |NAND_RE_BNAND_CLE| rowspan="3" |CPU.NAND_RE_BNAND_CLE| rowspan="3" |K19H21
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_RE_BRAWNAND_CLE
|-
|ALT1
|QSPI_B_DQSQSPI_B_SCLK
|-
|ALT5
|GPIO3_IO15GPIO3_IO05
|-
| rowspan="2" |J1.158138(NAND on board)| rowspan="2" |NAND_READY_BSD1_DATA0| rowspan="2" |CPU.NAND_READY_BSD1_DATA0| rowspan="2" |K20M25
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|RAWNAND_READY_BUSDHC1_DATA0|-|ALT5|GPIO2_IO02|-| rowspan="3" |J1.138(eMMC on board)| rowspan="3" |NAND_DATA00| rowspan="3" |CPU.NAND_DATA00| rowspan="3" |G20| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA00|-|ALT1|QSPI_A_DATA0
|-
|ALT5
|GPIO3_IO16GPIO3_IO06
|-
| rowspan="2" |J1.160140(NAND on board)| rowspan="2" |NAND_WE_BSD1_DATA1| rowspan="2" |CPU.NAND_WE_BSD1_DATA1| rowspan="2" |K22M24
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|RAWNAND_WE_BUSDHC1_DATA1|-|ALT5|GPIO2_IO0|-| rowspan="3" |J1.140(eMMC on board)| rowspan="3" |NAND_DATA01| rowspan="3" |CPU.NAND_DATA01| rowspan="3" |J20| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA01|-|ALT1|QSPI_A_DATA1
|-
|ALT5
|GPIO3_IO17GPIO3_IO07
|-
| rowspan="2" |J1.162142(NAND on board)| rowspan="2" |NAND_WP_BSD1_DATA2| rowspan="2" |CPU.NAND_WP_BSD1_DATA2| rowspan="2" |K21N25
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|RAWNAND_WP_BUSDHC1_DATA2
|-
|ALT5
|GPIO3_IO18GPIO2_IO04
|-
| rowspan="3" |J1.164142(eMMC on board)| rowspan="3" |NAND_DATA02| rowspan="3" |CPU.NAND_DATA02| rowspan="3" |H22| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA02|-|ALT1|QSPI_A_DATA2|-|ALT5|GPIO3_IO08|-| rowspan="2" |J1.144(NAND on board)| rowspan="2" |SD1_DATA3| rowspan="2" |CPU.SD1_DATA3| rowspan="2" |P25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA3|-|ALT5|GPIO2_IO05|-| rowspan="3" |J1.144(eMMC on board)| rowspan="3" |NAND_DATA03| rowspan="3" |CPU.NAND_DATA03| rowspan="3" |J21| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA03|-|ALT1|QSPI_A_DATA3|-|ALT5|GPIO3_IO09|-|J1.146
|DGND
|DGND
|G
|
| colspan="2" |
|-
|J1.166
|CLK1_N
|CPU.CLK1_N
|T23
|
|D
|
| colspan="2" |
|-
| rowspan="2" |J1.168148(NAND on board)|CLK1_Prowspan="2" |SD1_DATA4| rowspan="2" |CPU.CLK1_PSD1_DATA4|R23rowspan="2" |N24|rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|Drowspan="2" |I/O| colspanrowspan="2" ||ALT0|USDHC1_DATA4|-|ALT5|GPIO2_IO06
|-
| rowspan="3" |J1.170148(eMMC on board)|USB2_RXNrowspan="3" |NAND_DATA04| rowspan="3" |CPU.USB2_RX_NNAND_DATA04|B8rowspan="3" |L20|rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| colspanrowspan="23" ||ALT0|RAWNAND_DATA04
|-
|J1.172ALT1|USB2_RXP|CPU.USB2_RX_P|A8||D|| colspan="2" |QSPI_B_DATA0
|-
|J1.174ALT5|USB2_TXN|CPU.USB2_TX_N|B9||D|| colspan="2" |GPIO3_IO10
|-
| rowspan="2" |J1.176150(NAND on board)| rowspan="2" |USB2_TXPSD1_DATA5| rowspan="2" |CPU.USB2_TX_PSD1_DATA5|A9rowspan="2" |P24|rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|Drowspan="2" |I/O| colspanrowspan="2" ||ALT0|USDHC1_DATA5
|-
|J1.178ALT5|USB1_RXN|CPU.USB1_RX_N|B12||D|| colspan="2" |GPIO2_IO07
|-
| rowspan="3" |J1.180150(eMMC on board)|USB1_RXProwspan="3" |NAND_DATA05| rowspan="3" |CPU.USB1_RX_PNAND_DATA05|A12rowspan="3" |J22|rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| colspanrowspan="23" ||ALT0|RAWNAND_DATA05
|-
|J1.182ALT1|USB1_TXN|CPU.USB1_TX_N|B13||D|| colspan="2" |QSPI_B_DATA1
|-
|J1.184ALT5|USB1_TXP|CPU.USB1_TX_P|A13||D|| colspan="2" |GPIO3_IO11
|-
| rowspan="2" |J1.186152(NAND on board)| rowspan="2" |USB1_VBUSSD1_DATA6| rowspan="2" |CPU.USB1_VBUSSD1_DATA6|D14rowspan="2" |R25| -rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|Srowspan="2" |I/O| colspanrowspan="2" ||ALT0|USDHC1_DATA6
|-
|J1.188ALT5|USB2_VBUS|CPU.USB2_VBUS|D9| -|S|| colspan="2" |GPIO2_IO08
|-
| rowspan="3" |J1.190152(eMMC on board)|DGNDrowspan="3" |NAND_DATA06|DGNDrowspan="3" |CPU.NAND_DATA06| -rowspan="3" |L19|<nowiki>-</nowiki>rowspan="3" |NVCC_3V3|Growspan="3" |I/O| colspanrowspan="23" ||ALT0|RAWNAND_DATA06
|-
|J1.192ALT1|USB1_ID|CPU.USB1_ID|C14|VDD_PHY_3V3|I|| colspan="2" |QSPI_B_DATA2
|-
|J1.194ALT5|USB2_ID|CPU.USB2_ID|C9|VDD_PHY_3V3|I|| colspan="2" |GPIO3_IO12
|-
| rowspan="2" |J1.196154(NAND on board)| rowspan="2" |USB1_DNSD1_DATA7| rowspan="2" |CPU.USB1_DNSD1_DATA7|B14rowspan="2" |T25| -rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|Drowspan="2" |I/O| colspanrowspan="2" ||ALT0|USDHC1_DATA7
|-
|J1.198ALT5|USB1_DP|CPU.USB1_DP|A14| -|D|| colspan="2" |GPIO2_IO09
|-
| rowspan="3" |J1.200154(eMMC on board)|USB2_DProwspan="3" |NAND_DATA07| rowspan="3" |CPU.USB2_DPNAND_DATA07|A10rowspan="3" |M19| -rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| colspanrowspan="23" ||ALT0|RAWNAND_DATA07|-|ALT1|QSPI_B_DATA3|-|ALT5|GPIO3_IO13
|-
|J1.202156(NAND on board)|USB2_DNNAND_RE_B|CPU.USB2_DNNAND_RE_B|K19|B10NVCC_3V3| -I/O|DInternally used for NAND, do not connect
|
| colspan="2" |
|-
|J1.204
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| colspan="2" |
|-
|} ===Pinout Table J4 pins declaration ==={| class="wikitable" ! latexfontsizerowspan="scriptsize3" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! colspan="2" |Alternative Functions|-|J4J1.1|DGND|DGND| -|<nowiki>-</nowiki>|G156|| colspan="2" ||-| rowspan="7" |J4.2(eMMC on board)| rowspan="73" |SAI1_RXD7NAND_RE_B| rowspan="73" |CPU.SAI1_RXD7NAND_RE_B| rowspan="73" |G1K19| rowspan="73" |NVCC_3V3| rowspan="73" |I/O| rowspan="73" |internally used for BOOT config
|ALT0
|SAI1_RX_DATA7RAWNAND_RE_B
|-
|ALT1
|SAI6_MCLKQSPI_B_DQS
|-
|ALT2ALT5|SAI1_TX_SYNCGPIO3_IO15
|-
|ALT3J1.158(NAND on board)|NAND_READY_B|CPU.NAND_READY_B|K20|NVCC_3V3|I/O|Internally used for NAND, do not connect||SAI1_TX_DATA4
|-
|ALT4rowspan="2" |J1.158(eMMC on board)| rowspan="2" |NAND_READY_B| rowspan="2" |CPU.NAND_READY_B| rowspan="2" |K20| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|CORESIGHT_TRACE7RAWNAND_READY_B
|-
|ALT5
|GPIO4_IO09GPIO3_IO16
|-
|ALT6J1.160(NAND on board)|NAND_WE_B|CPU.NAND_WE_B|K22|NVCC_3V3|I/O|Internally used for NAND, do not connect||SRC_BOOT_CFG7
|-
| rowspan="62" |J4J1.3160(eMMC on board)| rowspan="62" |SAI1_RXD6NAND_WE_B| rowspan="62" |CPU.SAI1_RXD6NAND_WE_B| rowspan="62" |G2K22| rowspan="62" |NVCC_3V3| rowspan="62" |I/O| rowspan="62" |internally used for BOOT config
|ALT0
|SAI1_RX_DATA6RAWNAND_WE_B
|-
|ALT1ALT5|SAI6_TX_SYNCGPIO3_IO17
|-
|ALT2J1.162(NAND on board)|NAND_WP_B|CPU.NAND_WP_B|K21|NVCC_3V3|I/O|Internally used for NAND, do not connect||SAI6_RX_SYNC
|-
|ALT4rowspan="2" |J1.162(eMMC on board)| rowspan="2" |NAND_WP_B| rowspan="2" |CPU.NAND_WP_B| rowspan="2" |K21| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|CORESIGHT_TRACE6RAWNAND_WP_B
|-
|ALT5
|GPIO4_IO08|-|ALT6|SRC_BOOT_CFG6|-|J4.4|SAI1_RXD5|CPU.SAI1_RXD5|F1|NVCC_3V3|I/O|internally used for BOOT config|ALT0|SAI1_RX_DATA5GPIO3_IO18
|-
|J1.164
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J1.166
|CLK1_N
|CPU.CLK1_N
|T23
|
|D
|
|
|
|
|ALT1
|SAI6_TX_DATA0
|-
|J1.168
|CLK1_P
|CPU.CLK1_P
|R23
|
|D
|
|
|
|-
|J1.170
|USB2_RXN
|CPU.USB2_RX_N
|B8
|
|D
|
|
|
|ALT2
|SAI6_RX_DATA0
|-
|J1.172
|USB2_RXP
|CPU.USB2_RX_P
|A8
|
|D
|
|
|
|
|
|
|ALT3
|SAI1_RX_SYNC
|-
|J1.174
|USB2_TXN
|CPU.USB2_TX_N
|B9
|
|D
|
|
|
|-
|J1.176
|USB2_TXP
|CPU.USB2_TX_P
|A9
|
|D
|
|
|
|ALT4
|CORESIGHT_TRACE5
|-
|J1.178
|USB1_RXN
|CPU.USB1_RX_N
|B12
|
|D
|
|
|
|-
|J1.180
|USB1_RXP
|CPU.USB1_RX_P
|A12
|
|D
|
|
|
|ALT5
|GPIO4_IO07
|-
|J1.182
|USB1_TXN
|CPU.USB1_TX_N
|B13
|
|D
|
|
|
|-
|J1.184
|USB1_TXP
|CPU.USB1_TX_P
|A13
|
|D
|
|
|
|ALT6
|SRC_BOOT_CFG5
|-
|J4J1.5186|SAI1_RXD4USB1_VBUS|CPU.SAI1_RXD4USB1_VBUS|J1D14|NVCC_3V3-|I/OS|internally used for BOOT configAbsolute maximum ratings 5.25V
|
|
|-
|J4J1.6188|SAI1_RXD3USB2_VBUS|CPU.SAI1_RXD3USB2_VBUS|J2D9|NVCC_3V3-|I/OS|internally used for BOOT configAbsolute maximum ratings 5.25V
|
|
|-
|J4J1.7190|SAI1_RXD2DGND|CPU.SAI1_RXD2DGND|H2-|NVCC_3V3<nowiki>-</nowiki>|I/OG|internally used for BOOT config
|
|
|-
|J4J1.8192|SAI1_RXD1USB1_ID|CPU.SAI1_RXD1USB1_ID|L2C14|NVCC_3V3VDD_PHY_3V3|I/O|internally used for BOOT config
|
|
|-
|J4.9
|SAI1_RXD0
|CPU.SAI1_RXD0
|K2
|NVCC_3V3
|I/O
|internally used for BOOT config
|
|
|-
|J4J1.10194|SAI1_RXCUSB2_ID|CPU.SAI1_RXCUSB2_ID|K1C9|NVCC_3V3VDD_PHY_3V3|I/O
|
|
|
|-
|J4J1.11196|SAI1_RXFSUSB1_DN|CPU.SAI1_RXFSUSB1_DN|L1B14|NVCC_3V3-|I/OD
|
|
|
|-
|J4J1.12198|DGNDUSB1_DP|DGNDCPU.USB1_DP|A14
| -
|<nowiki>-</nowiki>|GD
|
|
|
|-
|J4J1.13200|SAI1_MCLKUSB2_DP|CPU.SAI1_MCLKUSB2_DP|A10|NVCC_3V3-|I/OD
|
|
|
|-
|J4J1.14202|USB2_DN|CPU.USB2_DN|B10| -|D||||-|J1.204
|DGND
|DGND
|
|-
|} ==ONE PIECE J4.15pins declaration =={|SAI1_TXFSclass="wikitable" ! latexfontsize="scriptsize" |CPU.SAI1_TXFSPin ! latexfontsize="scriptsize" |H4Pin Name! latexfontsize="scriptsize" |NVCC_3V3Internal Connections ! latexfontsize="scriptsize" |IBall/Opin # ! latexfontsize="scriptsize" | Voltage domain! latexfontsize="scriptsize" |Type ! latexfontsize="scriptsize" |Notes! colspan="2" |Alternative Functions
|-
|J4.161|SAI1_TXCDGND|CPU.SAI1_TXCDGND|J5-|NVCC_3V3<nowiki>-</nowiki>|I/OG
|
|
|
|-
| rowspan="7" |J4.172|SAI1_TXD0rowspan="7" |SAI1_RXD7| rowspan="7" |CPU.SAI1_TXD0SAI1_RXD7|F2rowspan="7" |G1| rowspan="7" |NVCC_3V3| rowspan="7" |I/O|internally rowspan="7" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_RX_DATA7
|-
|J4.18|SAI1_TXD1|CPU.SAI1_TXD1|E2|NVCC_3V3|I/O|internally used for BOOT config|ALT1|SAI6_MCLK
|-
|J4.19|SAI1_TXD2|CPU.SAI1_TXD2|B2|NVCC_3V3|I/O|internally used for BOOT config|ALT2|SAI1_TX_SYNC
|-
|J4.20|SAI1_TXD3|CPU.SAI1_TXD3|D1|NVCC_3V3|I/O|internally used for BOOT config|ALT3|SAI1_TX_DATA4
|-
|J4.21|SAI1_TXD4|CPU.SAI1_TXD4|D2|NVCC_3V3|I/O|internally used for BOOT config|ALT4|CORESIGHT_TRACE7
|-
|ALT5|GPIO4_IO09|-|ALT6|SRC_BOOT_CFG7|-| rowspan="6" |J4.223|SAI1_TXD5rowspan="6" |SAI1_RXD6| rowspan="6" |CPU.SAI1_TXD5SAI1_RXD6|C2rowspan="6" |G2| rowspan="6" |NVCC_3V3| rowspan="6" |I/O|internally rowspan="6" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_RX_DATA6
|-
|J4.23|SAI1_TXD6|CPU.SAI1_TXD6|B3|NVCC_3V3|I/O|internally used for BOOT config|ALT1|SAI6_TX_SYNC
|-
|J4.24|SAI1_TXD7|CPU.SAI1_TXD7|C1|NVCC_3V3|I/O|internally used for BOOT config|ALT2|SAI6_RX_SYNC
|-
|J4.25ALT4|DGND|DGND| -|<nowiki>-</nowiki>|G||||}===Pinout Table J5 pins declaration ==={| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! latexfontsize="scriptsize" | Alternative FunctionsCORESIGHT_TRACE6
|-
|J5.1ALT5|DGND|DGND| -|<nowiki>-</nowiki>|G| colspan="2" |GPIO4_IO08
|-
|J5.2ALT6|PCIE2_RXN|CPU.PCIE2_RXN_N|D24| -|D| colspan="2" |SRC_BOOT_CFG6
|-
|J5rowspan="7" |J4.34|PCIE2_RXProwspan="7" |SAI1_RXD5| rowspan="7" |CPU.PCIE2_RXN_PSAI1_RXD5|D25rowspan="7" |F1| -rowspan="7" |NVCC_3V3|Drowspan="7" |I/O| colspanrowspan="27" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_RX_DATA5
|-
|J5.4ALT1|DGNDSAI6_TX_DATA0|DGND| -|<nowiki>-</nowiki>|GALT2| colspan="2" |SAI6_RX_DATA0
|-
|J5.5ALT3|PCIE2_TXN|CPU.PCIE2_TXN_N|E24| -|D| colspan="2" |SAI1_RX_SYNC
|-
|J5.6ALT4|PCIE2_TXP|CPU.PCIE2_TXN_P|E25| -|D| colspan="2" |CORESIGHT_TRACE5
|-
|J5.7ALT5|DGND|DGND| -|<nowiki>-</nowiki>|G| colspan="2" |GPIO4_IO07
|-
|J5.8ALT6|PCIE2_REF_CLKN|CPU.PCIE2_REF_PAD_CLK_N|F24| -|D| colspan="2" |SRC_BOOT_CFG5
|-
|J5rowspan="6" |J4.95|PCIE2_REF_CLKProwspan="6" |SAI1_RXD4| rowspan="6" |CPU.PCIE2_REF_PAD_CLK_PSAI1_RXD4|F25rowspan="6" |J1| -rowspan="6" |NVCC_3V3|Drowspan="6" |I/O| colspanrowspan="26" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_RX_DATA4
|-
|J5.10ALT1|DGND|DGND| -|<nowiki>-</nowiki>|G| colspan="2" |SAI6_TX_BCLK
|-
|J5.11ALT2|CSI_P2_CKN|CPU.MIPI_CSI2_CLK_N|A19| -|D| colspan="2" |SAI6_RX_BCLK
|-
|J5.12ALT4|CSI_P2_CKP|CPU.MIPI_CSI2_CLK_P|B19| -|D| colspan="2" |CORESIGHT_TRACE4
|-
|J5.13ALT5|DGND|DGND| -|<nowiki>-</nowiki>|G| colspan="2" |GPIO4_IO06
|-
|J5.14ALT6|CSI_P2_DN0|CPU.MIPI_CSI2_D0_N|C20| -|D| colspan="2" |SRC_BOOT_CFG4
|-
|J5rowspan="5" |J4.156|CSI_P2_DP0rowspan="5" |SAI1_RXD3| rowspan="5" |CPU.MIPI_CSI2_D0_PSAI1_RXD3|D10rowspan="5" |J2| -rowspan="5" |NVCC_3V3|Drowspan="5" |I/O| colspanrowspan="25" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_RX_DATA3
|-
|J5.16ALT1|CSI_P2_DN1|CPU.MIPI_CSI2_D1_N|A20| -|D| colspan="2" |SAI5_RX_DATA3
|-
|J5.17ALT4|CSI_P2_DP1|CPU.MIPI_CSI2_D1_P|B20| -|D| colspan="2" |CORESIGHT_TRACE3
|-
|J5.18ALT5|DGND|DGND| -|<nowiki>-</nowiki>|G| colspan="2" |GPIO4_IO05
|-
|J5.19ALT6|CSI_P2_DN2|CPU.MIPI_CSI2_D2_N|A21| -|D| colspan="2" |SRC_BOOT_CFG3
|-
|J5rowspan="5" |J4.207|CSI_P2_DP2rowspan="5" |SAI1_RXD2| rowspan="5" |CPU.MIPI_CSI2_D2_PSAI1_RXD2|B21rowspan="5" |H2| -rowspan="5" |NVCC_3V3|Drowspan="5" |I/O| colspanrowspan="25" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_RX_DATA2
|-
|J5.21ALT1|CSI_P2_DN3|CPU.MIPI_CSI2_D3_N|C19| -|D| colspan="2" |SAI5_RX_DATA2
|-
|J5.22ALT4|CSI_P2_DP3|CPU.MIPI_CSI2_D3_P|D19| -|D| colspan="2" |CORESIGHT_TRACE2
|-
|J5.23ALT5|DGNDGPIO4_IO04|DGND| -|<nowiki>-</nowiki>|GALT6| colspan="2" |SRC_BOOT_CFG2
|-
|J5rowspan="5" |J4.248|I2C4_SCLrowspan="5" |SAI1_RXD1| rowspan="5" |CPU.I2C4_SCLSAI1_RXD1|F8rowspan="5" |L2| rowspan="5" |NVCC_3V3| rowspan="5" |I/O|rowspan="5" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_RX_DATA1
|-
|J5.25ALT1|I2C4_SDA|CPU.I2C4_SDA|F9|NVCC_3V3|I/O|||} ===Pinout Table JD5 pins declaration ==={| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! latexfontsize="scriptsize" | Alternative FunctionsSAI5_RX_DATA1
|-
|JD5.1ALT4|DGND|DGNDCORESIGHT_TRACE1| -|<nowiki>-</nowiki>|G|ALT5|GPIO4_IO03
|-
|JD5.2|EEPROM_WP|Internal EEPROM Write Protect| -|NVCC_3V3|I|ALT6|SRC_BOOT_CFG1
|-
|JD5rowspan="5" |J4.39| rowspan="5" |SAI1_RXD0|NCrowspan="5" |CPU.SAI1_RXD0|Not Connectedrowspan="5" |K2| -rowspan="5" |NVCC_3V3| -rowspan="5" |I/O|Zrowspan="5" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_RX_DATA0
|-
|JD5.4|JTAG_TCK|CPU.JTAG_TCK|T5|NVCC_3V3|I|internal pull-up 10k to NVCC_3V3ALT1|SAI5_RX_DATA0
|-
|JD5.5|JTAG_TMS|CPU.JTAG_TMS|V5|NVCC_3V3|I|ALT4|CORESIGHT_TRACE0
|-
|JD5.6|JTAG_TDO|CPU.JTAG_TDO|U5|NVCC_3V3|O|ALT5|GPIO4_IO02
|-
|JD5ALT6|SRC_BOOT_CFG0|-| rowspan="4" |J4.710|JTAG_TDIrowspan="4" |SAI1_RXC| rowspan="4" |CPU.JTAG_TDISAI1_RXC|W5rowspan="4" |K1| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI1_RX_BCLK|-|ALT1|SAI5_RX_BCLK|-|ALT4|CORESIGHT_TRACE_CTL|-|ALT5|GPIO4_IO01
|-
|JD5rowspan="4" |J4.811|JTAG_nTRSTrowspan="4" |SAI1_RXFS| rowspan="4" |CPU.JTAG_TRST_BSAI1_RXFS|U6rowspan="4" |L1| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI1_RX_SYNC
|-
|JD5.9|CPU_PORn|CPU.POR_BPMIC.RESETMCU|W203|NVCC_SNVS|I/O|internal pull-up 100k to NVCC_SNVSALT1|SAI5_RX_SYNC
|-
|JD5ALT4|CORESIGHT_TRACE_CLK|-|ALT5|GPIO4_IO00|-|J4.1012|DGND|DGND| -|<nowiki>-</nowiki>|G||||-| rowspan="4" |J4.13| rowspan="4" |SAI1_MCLK| rowspan="4" |CPU.SAI1_MCLK| rowspan="4" || rowspan="4" |NVCC_3V3|NVCC_3V3rowspan="4" |I/O| rowspan="4" ||ALT0|SAI1_MCLK|-|ALT1|SAI5_MCLK |-|ALT2|SAI1_TX_BCLK|-|ALT5|GPIO4_IO20|-|J4.14|DGND|DGND
| -
|<nowiki>-</nowiki>
|SG|
|
|
|-
| rowspan="4" |J4.15
| rowspan="4" |SAI1_TXFS
| rowspan="4" |CPU.SAI1_TXFS
| rowspan="4" |H4
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_TX_SYNC
|-
|ALT1
|SAI5_TX_SYNC
|-
|ALT4
|CORESIGHT_EVENTO
|-
|ALT5
|GPIO4_IO10
|-
| rowspan="4" |J4.16
| rowspan="4" |SAI1_TXC
| rowspan="4" |CPU.SAI1_TXC
| rowspan="4" |J5
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_TX_BCLK
|-
|ALT1
|SAI5_TX_BCLK
|-
|ALT4
|CORESIGHT_EVENTI
|-
|ALT5
|GPIO4_IO11
|-
| rowspan="5" |J4.17
| rowspan="5" |SAI1_TXD0
| rowspan="5" |CPU.SAI1_TXD0
| rowspan="5" |F2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA0
|-
|ALT1
|SAI5_TX_DATA0
|-
|ALT4
|CORESIGHT_TRACE8
|-
|ALT5
|GPIO4_IO12
|-
|ALT6
|SRC_BOOT_CFG8
|-
| rowspan="5" |J4.18
| rowspan="5" |SAI1_TXD1
| rowspan="5" |CPU.SAI1_TXD1
| rowspan="5" |E2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA1
|-
|ALT1
|SAI5_TX_DATA1
|-
|ALT4
|CORESIGHT_TRACE9
|-
|ALT5
|GPIO4_IO13
|-
|ALT6
|SRC_BOOT_CFG9
|-
| rowspan="5" |J4.19
| rowspan="5" |SAI1_TXD2
| rowspan="5" |CPU.SAI1_TXD2
| rowspan="5" |B2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA2
|-
|ALT1
|SAI5_TX_DATA2
|-
|ALT4
|CORESIGHT_TRACE10
|-
|ALT5
|GPIO4_IO14
|-
|ALT6
|SRC_BOOT_CFG10
|-
| rowspan="5" |J4.20
| rowspan="5" |SAI1_TXD3
| rowspan="5" |CPU.SAI1_TXD3
| rowspan="5" |D1
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA3
|-
|ALT1
|SAI5_TX_DATA3
|-
|ALT4
|CORESIGHT_TRACE11
|-
|ALT5
|GPIO4_IO15
|-
|ALT6
|SRC_BOOT_CFG11
|-
| rowspan="6" |J4.21
| rowspan="6" |SAI1_TXD4
| rowspan="6" |CPU.SAI1_TXD4
| rowspan="6" |D2
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA4
|-
|ALT1
|SAI6_RX_BCLK
|-
|ALT2
|SAI6_TX_BCLK
|-
|ALT4
|CORESIGHT_TRACE12
|-
|ALT5
|GPIO4_IO16
|-
|ALT6
|SRC_BOOT_CFG12
|-
| rowspan="6" |J4.22
| rowspan="6" |SAI1_TXD5
| rowspan="6" |CPU.SAI1_TXD5
| rowspan="6" |C2
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA5
|-
|ALT1
|SAI6_RX_DATA0
|-
|ALT2
|SAI6_TX_DATA0
|-
|ALT4
|CORESIGHT_TRACE13
|-
|ALT5
|GPIO4_IO17
|-
|ALT6
|SRC_BOOT_CFG13
|-
| rowspan="6" |J4.23
| rowspan="6" |SAI1_TXD6
| rowspan="6" |CPU.SAI1_TXD6
| rowspan="6" |B3
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA6
|-
|ALT1
|SAI6_RX_SYNC
|-
|ALT2
|SAI6_TX_SYNC
|-
|ALT4
|CORESIGHT_TRACE14
|-
|ALT5
|GPIO4_IO18
|-
|ALT6
|SRC_BOOT_CFG14
|-
| rowspan="5" |J4.24
| rowspan="5" |SAI1_TXD7
| rowspan="5" |CPU.SAI1_TXD7
| rowspan="5" |C1
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA7
|-
|ALT1
|SAI6_MCLK
|-
|ALT4
|CORESIGHT_TRACE15
|-
|ALT5
|GPIO4_IO19
|-
|ALT6
|SRC_BOOT_CFG15
|-
|J4.25
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|}
 
==ONE PIECE J5 pins declaration ==
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" | Voltage domain
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
! colspan="2" |Alternative Functions
|-
|J5.1
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.2
|PCIE2_RXN
|CPU.PCIE2_RXN_N
|D24
| -
|D
|
|
|
|-
|J5.3
|PCIE2_RXP
|CPU.PCIE2_RXN_P
|D25
| -
|D
|
|
|
|-
|J5.4
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.5
|PCIE2_TXN
|CPU.PCIE2_TXN_N
|E24
| -
|D
|
|
|
|-
|J5.6
|PCIE2_TXP
|CPU.PCIE2_TXN_P
|E25
| -
|D
|
|
|
|-
|J5.7
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.8
|PCIE2_REF_CLKN
|CPU.PCIE2_REF_PAD_CLK_N
|F24
| -
|D
|
|
|
|-
|J5.9
|PCIE2_REF_CLKP
|CPU.PCIE2_REF_PAD_CLK_P
|F25
| -
|D
|
|
|
|-
|J5.10
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.11
|CSI_P2_CKN
|CPU.MIPI_CSI2_CLK_N
|A19
| -
|D
|
|
|
|-
|J5.12
|CSI_P2_CKP
|CPU.MIPI_CSI2_CLK_P
|B19
| -
|D
|
|
|
|-
|J5.13
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.14
|CSI_P2_DN0
|CPU.MIPI_CSI2_D0_N
|C20
| -
|D
|
|
|
|-
|J5.15
|CSI_P2_DP0
|CPU.MIPI_CSI2_D0_P
|D10
| -
|D
|
|
|
|-
|J5.16
|CSI_P2_DN1
|CPU.MIPI_CSI2_D1_N
|A20
| -
|D
|
|
|
|-
|J5.17
|CSI_P2_DP1
|CPU.MIPI_CSI2_D1_P
|B20
| -
|D
|
|
|
|-
|J5.18
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.19
|CSI_P2_DN2
|CPU.MIPI_CSI2_D2_N
|A21
| -
|D
|
|
|
|-
|J5.20
|CSI_P2_DP2
|CPU.MIPI_CSI2_D2_P
|B21
| -
|D
|
|
|
|-
|J5.21
|CSI_P2_DN3
|CPU.MIPI_CSI2_D3_N
|C19
| -
|D
|
|
|
|-
|J5.22
|CSI_P2_DP3
|CPU.MIPI_CSI2_D3_P
|D19
| -
|D
|
|
|
|-
|J5.23
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
| rowspan="4" |J5.24
| rowspan="4" |I2C4_SCL
| rowspan="4" |CPU.I2C4_SCL
| rowspan="4" |F8
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|I2C4_SCL
|-
|ALT1
|PWM2_OUT
|-
|ALT2
|PCIE1_CLKREQ_B
|-
|ALT5
|GPIO5_IO20
|-
| rowspan="4" |J5.25
| rowspan="4" |I2C4_SDA
| rowspan="4" |CPU.I2C4_SDA
| rowspan="4" |F9
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|I2C4_SDA
|-
|ALT1
|PWM1_OUT
|-
|ALT2
|PCIE2_CLKREQ_B
|-
|ALT5
|GPIO5_IO21
|}
U0007
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