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MITO 8M SOM/MITO 8M Hardware/Pinout Table

11,930 bytes added, 17:49, 28 December 2023
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<section begin="History" />
{| style="border-collapse:collapse; "
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
|-
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0{{oldid| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" 10368|Sep 2020/09/29}}
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |2021/02/02
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |Add pull-up/down information
|-
|}
<section end="History" /><section begin="Body" />==Connectors and Pinout Table=====Introduction=description==
This chapter contains the pinout === Connectors description of ===In the following table are described all available connectors integrated on MITO 8M module, grouped in two tables (odd and even pins) that report the SOM:{| class="wikitable"|-!Connector name!Connector Type!Notes!Carrier board counterpart|-|J1|SODIMM edge connector 204 pin mapping of the 204|partially compatible with [[AXEL Lite SOM]]|TE Connectivity 2-2013289-1|-|J4|ONE PIECE connector single row 25pins||SAMTEC FSI-125-03-G-S-AD-TR|-|J5|ONE PIECE connector single row 25pins||SAMTEC FSI-125-03-G-S-pin SOAD-DIMM TR|}The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to MITO 8M connectorpinout specifications.See the images below for reference:
[[File:MITO 8M-conn-TOP.png|500px|thumb|MITO 8M TOP view|none]]
[[File:MITO 8M-conn-BOTTOM.png|500px|thumb|MITO 8M BOTTOM view|none]]
 
Below a detailed description of the pinout, grouped in the following tables:
* two tables (ODD and EVEN pins) that report the pin mapping of the 204-pin SO-DIMM edge
* a dedicated tables for J4 one-piece connector
* a dedicated tables for J5 one-piece connector
 
=== Pinout Table description ===
Each row in the pinout tables contains the following information:
 {| class="wikitable" style="width:50%;"
|-
|'''Pin'''
|-
|'''Pin Name'''
| Pin (signal) name on the AxelLite MITO 8M connectors
|-
|'''Internal<br>connections'''
| Connections to the Axel Ultra components
* CPU.<x> : pin connected to CPU pad named <x>
* PMIC.<x> : pin connected to the Power Manager IC(NXP PF4210)* LAN.<x> : pin connected to the LAN PHY(MICROCHIP KSZ9031RNX)* BRIDGE.<x> : pin connected to the MIPI-to-LVDS bridge* SV.<x>: pin connected to voltage supervisor(TI SN65DSI84)
|-
|'''Ball/pin #'''
|}
===Pinout Table SODIMM J1 ODD pins declaration ===
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|NVCC_1V8
|I/O
|must Must be level translated if used @ 3V3Internally pulled-up to 1.8V during bootstrap
|
|
|NVCC_1V8
|I/O
|must Must be level translated if used @ 3V3Internally pulled-up to 1.8V during bootstrap
|
|
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for ETH PHY reset, do not connect
|ALT0
|GPIO1_IO01
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |Internally used, do not connect
|ALT0
|GPIO1_IO13
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |Internally used for MIPI-to-LVDS interrupt, do not connectPulled-up to NVCC_3V3
|ALT0
|GPIO1_IO05
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for MIPI-to-LVDS enable, do not connect
|ALT0
|GPIO1_IO06
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|DGND
| -
|<nowiki>-</nowiki>
|G
|
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="63" |used as default Linux console
|ALT0
|UART2_TX
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |used as default Linux console
|ALT0
|UART2_RXD
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|}
===Pinout Table SODIMM J1 EVEN pins declaration ===
{| class="wikitable"
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for SW reset, do not connect
|ALT0
|GPIO1_IO02
|-
| rowspan="2" |J1.54
| rowspan="2" |SD1_STROBEGPIO1_IO10| rowspan="2" |CPU.SD1_STROBEGPIO1_IO10| rowspan="2" |T24M7| rowspan="2" |NVCC_1V8(NVCC_3V3 on request)
| rowspan="2" |I/O
| rowspan="2" |internally Internally used for eMMC(available on NAND storage SOM) ???ETH PHY interrupt, do not connect
|ALT0
|USDHC1_STROBE GPIO1_IO10
|-
|ALT5ALT1|GPIO2_IO11USB1_OTG_ID
|-
|J1.56
|VDDA_1V8
|D
|Internally used for PCIe CLK, do not connect
|
|
|VDDA_1V8
|D
|Internally used for PCIe CLK, do not connect
|
|
|-
|J1.124
(NAND on board)
|NAND_DQS
|CPU.NAND_DQS
|NVCC_3V3
|I/O
|internally Internally used for NAND, do not connect
|
|
|-
| rowspan="3" |J1.124
(eMMC on board)
| rowspan="3" |NAND_DQS
| rowspan="3" |CPU.NAND_DQS
| rowspan="3" |M20
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|RAWNAND_DQS
|-
|ALT1
|QSPI_A_DQS
|-
|ALT5
|GPIO3_IO14
|-
|J1.126
(NAND on board)
|NAND_ALE
|CPU.NAND_ALE
|NVCC_3V3
|I/O
|internally Internally used for NAND, do not connect
|
|
|-
| rowspan="3" |J1.128126(eMMC on board)|NAND_CE0_B // SD1_CLKrowspan="3" |NAND_ALE| rowspan="3" |CPU.NAND_CE0_B // CPU.SD1_CLKNAND_ALE|H19 // L25rowspan="3" |G19|NVCC_1V8 // rowspan="3" |NVCC_3V3 ???| rowspan="3" |I/O|???rowspan="3" ||ALT0|RAWNAND_ALE
|-
|J1.130|NAND_CE1_B // SD1_CMD|CPU.NAND_CE1_B // CPU.SD1_CMD|G21 // L24|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT1|QSPI_A_SCLK
|-
|J1.132|NAND_CE2_B // SD1_RST_B|CPU.NAND_CE2_B // CPU.SD1_RST_B|F21 // R24|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT5|GPIO3_IO00
|-
| rowspan="2" |J1.134128(NAND on board)|NAND_CE3_B // SD1_STROBErowspan="2" |SD1_CLK| rowspan="2" |CPU.NAND_CE3_B // CPU.SD1_STROBESD1_CLK|H20 // T24rowspan="2" |L25|rowspan="2" |NVCC_3V3(NVCC_1V8 // NVCC_3V3 ???on request)| rowspan="2" |I/O|???rowspan="2" ||ALT0|USDHC1_CLK|-|ALT5|GPIO2_IO00
|-
| rowspan="3" |J1.136128(eMMC on board)|NAND_CLErowspan="3" |NAND_CE0_B|DGNDrowspan="3" |CPU.NAND_CE0_B|H21rowspan="3" |H19| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_CE0_B
|-
|J1.138|NAND_DATA00 // SD1_DATA0|CPU.NAND_DATA00 // CPU.SD1_DATA0|G20 // M25|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT1|QSPI_A_SS0_B
|-
|J1.140|NAND_DATA01 // SD1_DATA1|CPU.NAND_DATA01 // CPU.SD1_DATA1|J20 // M24|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT5|GPIO3_IO01
|-
| rowspan="2" |J1.142130(NAND on board)| rowspan="2" |NAND_DATA02 // SD1_DATA2SD1_CMD| rowspan="2" |CPU.NAND_DATA02 // CPU.SD1_DATA2SD1_CMD|H22 // N25rowspan="2" |L24|rowspan="2" |NVCC_3V3(NVCC_1V8 // NVCC_3V3 ???on request)| rowspan="2" |I/O|???rowspan="2" ||ALT0|USDHC1_CMD
|-
|J1.144|NAND_DATA03 // SD1_DATA3|CPU.NAND_DATA03 // CPU.SD1_DATA3|J21 // P25|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT5|GPIO2_IO01
|-
| rowspan="3" |J1.146130(eMMC on board)| rowspan="3" |DGNDNAND_CE1_B|DGNDrowspan="3" |CPU.NAND_CE1_B| -rowspan="3" |G21|<nowiki>-<rowspan="3" |NVCC_3V3| rowspan="3" |I/nowiki>O|Growspan="3" ||ALT0|RAWNAND_CE1_B
|-
|J1.148|NAND_DATA04 // SD1_DATA4|CPU.NAND_DATA04 // CPU.SD1_DATA4|L20 // N24|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT1|QSPI_A_SS1_B
|-
|J1.150|NAND_DATA05 // SD1_DATA5|CPU.NAND_DATA05 // CPU.SD1_DATA5|J22 // P24|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT5|GPIO3_IO02
|-
| rowspan="2" |J1.152132(NAND on board)| rowspan="2" |NAND_DATA06 // SD1_DATA6SD1_RST_B| rowspan="2" |CPU.NAND_DATA06 // CPU.SD1_DATA6SD1_RST_B|L19 // R25rowspan="2" |R24|rowspan="2" |NVCC_3V3(NVCC_1V8 // NVCC_3V3 ???on request)| rowspan="2" |I/O|???rowspan="2" ||ALT0|USDHC1_RESET_B
|-
|J1.154|NAND_DATA07 // SD1_DATA7|CPU.NAND_DATA07 // CPU.SD1_DATA7|M19 // T25|NVCC_1V8 // NVCC_3V3 ???|I/O|???|ALT5|GPIO2_IO10
|-
| rowspan="3" |J1.132(eMMC on board)| rowspan="3" |NAND_CE2_B| rowspan="3" |CPU.NAND_CE2_B| rowspan="3" |F21| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_CE2_B|-|ALT1|QSPI_B_SS0_B|-|ALT5|GPIO3_IO03|-| rowspan="2" |J1.134(NAND on board)| rowspan="2" |SD1_STROBE| rowspan="2" |CPU.SD1_STROBE| rowspan="2" |T24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_STROBE|-|ALT5|GPIO2_IO11|-| rowspan="3" |J1.134(eMMC on board)| rowspan="3" |NAND_CE3_B| rowspan="3" |CPU.NAND_CE3_B| rowspan="3" |H20| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_CE3_B|-|ALT1|QSPI_B_SS1_B|-|ALT5|GPIO3_IO034|-|J1.156136(NAND on board)|NAND_RE_BNAND_CLE|CPU.NAND_RE_BNAND_CLE|K19H21
|NVCC_3V3
|I/O
|Internally used for NAND, do not connect
|
|
|-
| rowspan="3" |J1.158136(eMMC on board)|NAND_READY_Browspan="3" |NAND_CLE| rowspan="3" |CPU.NAND_READY_BNAND_CLE|K20rowspan="3" |H21| rowspan="3" |NVCC_3V3| rowspan="3" |I/O|rowspan="3" ||ALT0|RAWNAND_CLE|-|ALT1|QSPI_B_SCLK
|-
|J1.160|NAND_WE_B|CPU.NAND_WE_B|K22|NVCC_3V3|I/O||ALT5|GPIO3_IO05
|-
| rowspan="2" |J1.162138(NAND on board)|NAND_WP_Browspan="2" |SD1_DATA0| rowspan="2" |CPU.NAND_WP_BSD1_DATA0|K21rowspan="2" |M25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA0
|-
|ALT5|GPIO2_IO02|-| rowspan="3" |J1.164138(eMMC on board)| rowspan="3" |NAND_DATA00|DGNDrowspan="3" |CPU.NAND_DATA00|DGNDrowspan="3" |G20| -rowspan="3" |NVCC_3V3|<nowiki>-<rowspan="3" |I/nowiki>O|Growspan="3" ||ALT0|RAWNAND_DATA00
|-
|J1.166|CLK1_N|CPU.CLK1_N|T23||D||ALT1|QSPI_A_DATA0
|-
|J1.168|CLK1_P|CPU.CLK1_P|R23||D||ALT5|GPIO3_IO06
|-
| rowspan="2" |J1.170140(NAND on board)| rowspan="2" |USB2_RXNSD1_DATA1| rowspan="2" |CPU.USB2_RX_NSD1_DATA1| rowspan="2" |M24| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA1|-|B8ALT5|GPIO2_IO0|D-| rowspan="3" |J1.140(eMMC on board)| rowspan="3" |NAND_DATA01| rowspan="3" |CPU.NAND_DATA01| rowspan="3" |J20| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA01
|-
|J1.172|USB2_RXP|CPU.USB2_RX_P|A8||D||ALT1|QSPI_A_DATA1
|-
|J1.174|USB2_TXN|CPU.USB2_TX_N|B9||D||ALT5|GPIO3_IO07
|-
| rowspan="2" |J1.176142(NAND on board)|USB2_TXProwspan="2" |SD1_DATA2| rowspan="2" |CPU.USB2_TX_PSD1_DATA2| rowspan="2" |N25|A9rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|DUSDHC1_DATA2|-|ALT5|GPIO2_IO04
|-
| rowspan="3" |J1.178142(eMMC on board)|USB1_RXNrowspan="3" |NAND_DATA02| rowspan="3" |CPU.USB1_RX_NNAND_DATA02|B12rowspan="3" |H22|rowspan="3" |NVCC_3V3|Drowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA02
|-
|J1.180|USB1_RXP|CPU.USB1_RX_P|A12||D||ALT1|QSPI_A_DATA2
|-
|ALT5|GPIO3_IO08|-| rowspan="2" |J1.182144(NAND on board)|USB1_TXNrowspan="2" |SD1_DATA3| rowspan="2" |CPU.USB1_TX_NSD1_DATA3| rowspan="2" |P25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA3|-|ALT5|GPIO2_IO05|-| rowspan="3" |J1.144(eMMC on board)| rowspan="3" |NAND_DATA03| rowspan="3" |CPU.NAND_DATA03| rowspan="3" |J21| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA03|B13-|ALT1|DQSPI_A_DATA3|-|ALT5|GPIO3_IO09
|-
|J1.184146|USB1_TXPDGND|CPU.USB1_TX_PDGND|A13-|<nowiki>-</nowiki>|DG
|
|
|
|-
| rowspan="2" |J1.186148(NAND on board)|USB1_VBUSrowspan="2" |SD1_DATA4| rowspan="2" |CPU.USB1_VBUSSD1_DATA4|D14rowspan="2" |N24| -rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|SUSDHC1_DATA4|-|ALT5|GPIO2_IO06
|-
| rowspan="3" |J1.188148(eMMC on board)|USB2_VBUSrowspan="3" |NAND_DATA04| rowspan="3" |CPU.USB2_VBUSNAND_DATA04|D9rowspan="3" |L20| -rowspan="3" |NVCC_3V3|Srowspan="3" |I/O| rowspan="3" ||ALT0|RAWNAND_DATA04
|-
|J1.190|DGND|DGND| -|<nowiki>-</nowiki>|G||ALT1|QSPI_B_DATA0
|-
|J1.192|USB1_ID|CPU.USB1_ID|C14|VDD_PHY_3V3|I||ALT5|GPIO3_IO10
|-
| rowspan="2" |J1.194150(NAND on board)|USB2_IDrowspan="2" |SD1_DATA5| rowspan="2" |CPU.USB2_IDSD1_DATA5|C9rowspan="2" |P24|VDD_PHY_3V3rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA5
|-
|J1.196|USB1_DN|CPU.USB1_DN|B14| -|D||ALT5|GPIO2_IO07
|-
| rowspan="3" |J1.198150(eMMC on board)|USB1_DProwspan="3" |NAND_DATA05| rowspan="3" |CPU.USB1_DPNAND_DATA05| rowspan="3" |J22| rowspan="3" |NVCC_3V3| rowspan="3" |I/O|A14rowspan="3" || -ALT0|DRAWNAND_DATA05|-|ALT1|QSPI_B_DATA1
|-
|J1.200|USB2_DP|CPU.USB2_DP|A10| -|D||ALT5|GPIO3_IO11
|-
| rowspan="2" |J1.202152(NAND on board)|USB2_DNrowspan="2" |SD1_DATA6| rowspan="2" |CPU.USB2_DNSD1_DATA6|B10rowspan="2" |R25| -rowspan="2" |NVCC_3V3(NVCC_1V8 on request)|Drowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA6
|-
|J1.204|DGND|DGND| -|<nowiki>-</nowiki>|G||ALT5|GPIO2_IO08
|-
|} ===Pinout Table J4 pins declaration ==={| classrowspan="wikitable3" |J1.152! latexfontsize(eMMC on board)| rowspan="scriptsize3" | Pin NAND_DATA06! latexfontsize| rowspan="scriptsize3" | Pin NameCPU.NAND_DATA06! latexfontsize| rowspan="scriptsize3" | Internal Connections L19! latexfontsize| rowspan="scriptsize3" | Ball/pin # NVCC_3V3! latexfontsize| rowspan="scriptsize3" |<nowiki> Voltage|domain<I/nowiki>O! latexfontsize| rowspan="scriptsize3" | Type ! latexfontsize="scriptsize" | NotesALT0! latexfontsize="scriptsize" | Alternative FunctionsRAWNAND_DATA06
|-
|J4.1|DGND|DGND| -|<nowiki>-</nowiki>|G|ALT1|QSPI_B_DATA2
|-
|J4.2|SAI1_RXD7|CPU.SAI1_RXD7|G1|NVCC_3V3|I/O|internally used for BOOT configALT5|GPIO3_IO12
|-
|J4rowspan="2" |J1.154(NAND on board)| rowspan="2" |SD1_DATA7| rowspan="2" |CPU.SD1_DATA7| rowspan="2" |T25| rowspan="2" |NVCC_3V3(NVCC_1V8 on request)| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC1_DATA7|-|ALT5|GPIO2_IO09|-| rowspan="3" |J1.154(eMMC on board)|SAI1_RXD6rowspan="3" |NAND_DATA07| rowspan="3" |CPU.SAI1_RXD6NAND_DATA07|G2rowspan="3" |M19| rowspan="3" |NVCC_3V3| rowspan="3" |I/O|internally used for BOOT configrowspan="3" ||ALT0|RAWNAND_DATA07|-|ALT1|QSPI_B_DATA3|-|ALT5|GPIO3_IO13
|-
|J4J1.4156(NAND on board)|SAI1_RXD5NAND_RE_B|CPU.SAI1_RXD5NAND_RE_B|F1K19
|NVCC_3V3
|I/O
|internally Internally used for BOOT configNAND, do not connect|
|
|-
|J4rowspan="3" |J1.5156(eMMC on board)|SAI1_RXD4rowspan="3" |NAND_RE_B| rowspan="3" |CPU.SAI1_RXD4NAND_RE_B|J1rowspan="3" |K19| rowspan="3" |NVCC_3V3| rowspan="3" |I/O|internally used for BOOT configrowspan="3" ||ALT0|RAWNAND_RE_B|-|ALT1|QSPI_B_DQS|-|ALT5|GPIO3_IO15
|-
|J4J1.6158(NAND on board)|SAI1_RXD3NAND_READY_B|CPU.SAI1_RXD3NAND_READY_B|J2K20
|NVCC_3V3
|I/O
|internally Internally used for BOOT configNAND, do not connect
|
|-
|J4.7
|SAI1_RXD2
|CPU.SAI1_RXD2
|H2
|NVCC_3V3
|I/O
|internally used for BOOT config
|
|-
|J4rowspan="2" |J1.8158(eMMC on board)|SAI1_RXD1rowspan="2" |NAND_READY_B| rowspan="2" |CPU.SAI1_RXD1NAND_READY_B|L2rowspan="2" |K20| rowspan="2" |NVCC_3V3| rowspan="2" |I/O|internally used for BOOT configrowspan="2" ||ALT0|RAWNAND_READY_B
|-
|J4.9|SAI1_RXD0|CPU.SAI1_RXD0|K2|NVCC_3V3|I/O|internally used for BOOT configALT5|GPIO3_IO16
|-
|J4J1.10160(NAND on board)|SAI1_RXCNAND_WE_B|CPU.SAI1_RXCNAND_WE_B|K1K22
|NVCC_3V3
|I/O
|Internally used for NAND, do not connect
|
|
|-
|J4rowspan="2" |J1.160(eMMC on board)| rowspan="2" |NAND_WE_B| rowspan="2" |CPU.NAND_WE_B| rowspan="2" |K22| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|RAWNAND_WE_B|-|ALT5|GPIO3_IO17|-|J1.11162(NAND on board)|SAI1_RXFSNAND_WP_B|CPU.SAI1_RXFSNAND_WP_B|L1K21
|NVCC_3V3
|I/O
|Internally used for NAND, do not connect
|
|
|-
|J4rowspan="2" |J1.12162(eMMC on board)| rowspan="2" |NAND_WP_B| rowspan="2" |CPU.NAND_WP_B| rowspan="2" |K21| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|RAWNAND_WP_B|-|ALT5|GPIO3_IO18|-|J1.164
|DGND
|DGND
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J4J1.13166|SAI1_MCLKCLK1_N|CPU.SAI1_MCLKCLK1_N|T23||D
|
|NVCC_3V3
|I/O
|
|
|-
|J4J1.14168|DGNDCLK1_P|DGND| -|<nowiki>-</nowiki>CPU.CLK1_P|GR23
|
|D
|
|-
|J4.15
|SAI1_TXFS
|CPU.SAI1_TXFS
|H4
|NVCC_3V3
|I/O
|
|
|-
|J4J1.16170|SAI1_TXCUSB2_RXN|CPU.SAI1_TXCUSB2_RX_N|J5|NVCC_3V3|I/OB8
|
|D
|
|-
|J4.17
|SAI1_TXD0
|CPU.SAI1_TXD0
|F2
|NVCC_3V3
|I/O
|internally used for BOOT config
|
|-
|J4.18
|SAI1_TXD1
|CPU.SAI1_TXD1
|E2
|NVCC_3V3
|I/O
|internally used for BOOT config
|
|-
|J4J1.19172|SAI1_TXD2USB2_RXP|CPU.SAI1_TXD2USB2_RX_P|B2|NVCC_3V3|I/O|internally used for BOOT configA8
|
|-|J4.20|SAI1_TXD3|CPU.SAI1_TXD3|D1|NVCC_3V3|I/O|internally used for BOOT configD
|
|-
|J4.21
|SAI1_TXD4
|CPU.SAI1_TXD4
|D2
|NVCC_3V3
|I/O
|internally used for BOOT config
|
|-
|J4.22
|SAI1_TXD5
|CPU.SAI1_TXD5
|C2
|NVCC_3V3
|I/O
|internally used for BOOT config
|
|-
|J4J1.23174|SAI1_TXD6USB2_TXN|CPU.SAI1_TXD6USB2_TX_N|B3|NVCC_3V3|I/O|internally used for BOOT configB9
|
|-|J4.24|SAI1_TXD7|CPU.SAI1_TXD7|C1|NVCC_3V3|I/O|internally used for BOOT configD
|
|-
|J4.25
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|}===Pinout Table J5 pins declaration ==={| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! latexfontsize="scriptsize" | Alternative Functions|-|J5J1.1176|DGNDUSB2_TXP|DGND| -|<nowiki>-</nowiki>CPU.USB2_TX_P|GA9
|
|D
|
|-
|J5.2
|PCIE2_RXN
|CPU.PCIE2_RXN_N
|D24
| -
|D
|
|
|-
|J5J1.3178|PCIE2_RXPUSB1_RXN|CPU.PCIE2_RXN_PUSB1_RX_N|D25B12| -
|D
|
|
|
|-
|J5J1.4180|DGNDUSB1_RXP|DGNDCPU.USB1_RX_P|A12| -|<nowiki>-</nowiki>D|G
|
|
|-
|J5J1.5182|PCIE2_TXNUSB1_TXN|CPU.PCIE2_TXN_NUSB1_TX_N|E24B13| -
|D
|
|
|
|-
|J5J1.6184|PCIE2_TXPUSB1_TXP|CPU.PCIE2_TXN_PUSB1_TX_P|E25A13| -
|D
|
|
|
|-
|J5J1.7186|DGNDUSB1_VBUS|DGNDCPU.USB1_VBUS|D14
| -
|<nowiki>-</nowiki>S|GAbsolute maximum ratings 5.25V
|
|
|-
|J5J1.8188|PCIE2_REF_CLKNUSB2_VBUS|CPU.PCIE2_REF_PAD_CLK_NUSB2_VBUS|F24D9
| -
|DS|Absolute maximum ratings 5.25V
|
|
|-
|J5J1.9|PCIE2_REF_CLKP|CPU.PCIE2_REF_PAD_CLK_P|F25| -|D|||-|J5.10190
|DGND
|DGND
|G
|
|
|-
|J5.11
|CSI_P2_CKN
|CPU.MIPI_CSI2_CLK_N
|A19
| -
|D
|
|
|-
|J5J1.12192|CSI_P2_CKPUSB1_ID|CPU.MIPI_CSI2_CLK_PUSB1_ID|B19C14| -VDD_PHY_3V3|I|D
|
|
|-
|J5J1.13194|DGNDUSB2_ID|DGNDCPU.USB2_ID|C9| -VDD_PHY_3V3|<nowiki>-</nowiki>I|G
|
|
|-
|J5J1.14196|CSI_P2_DN0USB1_DN|CPU.MIPI_CSI2_D0_NUSB1_DN|C20B14
| -
|D
|
|
|
|-
|J5J1.15198|CSI_P2_DP0USB1_DP|CPU.MIPI_CSI2_D0_PUSB1_DP|D10A14
| -
|D
|
|
|
|-
|J5J1.16200|CSI_P2_DN1USB2_DP|CPU.MIPI_CSI2_D1_NUSB2_DP|A20A10
| -
|D
|
|
|
|-
|J5J1.17202|CSI_P2_DP1USB2_DN|CPU.MIPI_CSI2_D1_PUSB2_DN|B20B10
| -
|D
|
|
|
|-
|J5J1.18204
|DGND
|DGND
|G
|
|
|-
|J5.19
|CSI_P2_DN2
|CPU.MIPI_CSI2_D2_N
|A21
| -
|D
|
|
|-
|J5.20} ==ONE PIECE J4 pins declaration =={| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" |CSI_P2_DP2Pin Name! latexfontsize="scriptsize" |CPU.MIPI_CSI2_D2_PInternal Connections ! latexfontsize="scriptsize" |B21Ball/pin # ! latexfontsize="scriptsize" | -Voltage domain! latexfontsize="scriptsize" |DType ! latexfontsize="scriptsize" |Notes! colspan="2" |Alternative Functions
|-
|J5J4.21|CSI_P2_DN3|CPU.MIPI_CSI2_D3_N|C19| -|D|||-|J5.22|CSI_P2_DP3|CPU.MIPI_CSI2_D3_P|D19| -|D|||-|J5.231
|DGND
|DGND
|
|
|
|-
| rowspan="7" |J4.2
| rowspan="7" |SAI1_RXD7
| rowspan="7" |CPU.SAI1_RXD7
| rowspan="7" |G1
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_RX_DATA7
|-
|J5.24|I2C4_SCL|CPU.I2C4_SCL|F8|NVCC_3V3|I/O|ALT1|SAI6_MCLK
|-
|J5.25ALT2|I2C4_SDA|CPU.I2C4_SDA|F9|NVCC_3V3|I/O|||} ===Pinout Table JD5 pins declaration ==={| class="wikitable" ! latexfontsize="scriptsize" | Pin ! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! latexfontsize="scriptsize" | Alternative FunctionsSAI1_TX_SYNC
|-
|JD5.1|DGND|DGND| -|<nowiki>-</nowiki>|G|ALT3|SAI1_TX_DATA4
|-
|JD5.2|EEPROM_WP|Internal EEPROM Write Protect| -|NVCC_3V3|I|ALT4|CORESIGHT_TRACE7
|-
|JD5ALT5|GPIO4_IO09|-|ALT6|SRC_BOOT_CFG7|-| rowspan="6" |J4.3|NCrowspan="6" |SAI1_RXD6|Not Connectedrowspan="6" |CPU.SAI1_RXD6| -rowspan="6" |G2| rowspan="6" |NVCC_3V3| -rowspan="6" |I/O|Zrowspan="6" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_RX_DATA6
|-
|JD5.4|JTAG_TCK|CPU.JTAG_TCK|T5|NVCC_3V3|I|internal pull-up 10k to NVCC_3V3ALT1|SAI6_TX_SYNC
|-
|JD5.5|JTAG_TMS|CPU.JTAG_TMS|V5|NVCC_3V3|I|ALT2|SAI6_RX_SYNC
|-
|JD5.6|JTAG_TDO|CPU.JTAG_TDO|U5|NVCC_3V3|O|ALT4|CORESIGHT_TRACE6
|-
|JD5.7|JTAG_TDI|CPU.JTAG_TDI|W5|NVCC_3V3|I|ALT5|GPIO4_IO08
|-
|JD5.8|JTAG_nTRST|CPU.JTAG_TRST_B|U6|NVCC_3V3|I|ALT6|SRC_BOOT_CFG6
|-
|JD5rowspan="7" |J4.4| rowspan="7" |SAI1_RXD5| rowspan="7" |CPU.SAI1_RXD5| rowspan="7" |F1| rowspan="7" |NVCC_3V3| rowspan="7" |I/O| rowspan="7" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_RX_DATA5|-|ALT1|SAI6_TX_DATA0|-|ALT2|SAI6_RX_DATA0|-|ALT3|SAI1_RX_SYNC|-|ALT4|CORESIGHT_TRACE5|-|ALT5|GPIO4_IO07|-|ALT6|SRC_BOOT_CFG5|-| rowspan="6" |J4.95|CPU_PORnrowspan="6" |SAI1_RXD4| rowspan="6" |CPU.POR_BSAI1_RXD4| rowspan="6" |J1| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_RX_DATA4|-|ALT1|SAI6_TX_BCLK|-|ALT2|SAI6_RX_BCLK|-|ALT4|CORESIGHT_TRACE4|-PMIC|ALT5|GPIO4_IO06|-|ALT6|SRC_BOOT_CFG4|-| rowspan="5" |J4.RESETMCU6| rowspan="5" |SAI1_RXD3|W20rowspan="5" |CPU.SAI1_RXD33| rowspan="5" |J2|NVCC_SNVSrowspan="5" |NVCC_3V3| rowspan="5" |I/O|internal pullrowspan="5" |Internally used for BOOT configCould be pulled-up 100k to NVCC_SNVSor down during bootstrap.|ALT0|SAI1_RX_DATA3|-|ALT1|SAI5_RX_DATA3
|-
|JD5ALT4|CORESIGHT_TRACE3|-|ALT5|GPIO4_IO05|-|ALT6|SRC_BOOT_CFG3|-| rowspan="5" |J4.7| rowspan="5" |SAI1_RXD2| rowspan="5" |CPU.SAI1_RXD2| rowspan="5" |H2| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_RX_DATA2|-|ALT1|SAI5_RX_DATA2|-|ALT4|CORESIGHT_TRACE2|-|ALT5|GPIO4_IO04|-|ALT6|SRC_BOOT_CFG2|-| rowspan="5" |J4.8| rowspan="5" |SAI1_RXD1| rowspan="5" |CPU.SAI1_RXD1| rowspan="5" |L2| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_RX_DATA1|-|ALT1|SAI5_RX_DATA1|-|ALT4|CORESIGHT_TRACE1|-|ALT5|GPIO4_IO03|-|ALT6|SRC_BOOT_CFG1|-| rowspan="5" |J4.9| rowspan="5" |SAI1_RXD0| rowspan="5" |CPU.SAI1_RXD0| rowspan="5" |K2| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" |Internally used for BOOT configCould be pulled-up or down during bootstrap.|ALT0|SAI1_RX_DATA0|-|ALT1|SAI5_RX_DATA0|-|ALT4|CORESIGHT_TRACE0|-|ALT5|GPIO4_IO02|-|ALT6|SRC_BOOT_CFG0|-| rowspan="4" |J4.10| rowspan="4" |SAI1_RXC| rowspan="4" |CPU.SAI1_RXC| rowspan="4" |K1| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI1_RX_BCLK|-|ALT1|SAI5_RX_BCLK|-|ALT4|CORESIGHT_TRACE_CTL|-|ALT5|GPIO4_IO01|-| rowspan="4" |J4.11| rowspan="4" |SAI1_RXFS| rowspan="4" |CPU.SAI1_RXFS| rowspan="4" |L1| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI1_RX_SYNC|-|ALT1|SAI5_RX_SYNC|-|ALT4|CORESIGHT_TRACE_CLK|-|ALT5|GPIO4_IO00|-|J4.12|DGND|DGND| -|<nowiki>-</nowiki>|SG|
|
|
|-
| rowspan="4" |J4.13
| rowspan="4" |SAI1_MCLK
| rowspan="4" |CPU.SAI1_MCLK
| rowspan="4" |
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_MCLK
|-
|ALT1
|SAI5_MCLK
|-
|ALT2
|SAI1_TX_BCLK
|-
|ALT5
|GPIO4_IO20
|-
|J4.14
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
| rowspan="4" |J4.15
| rowspan="4" |SAI1_TXFS
| rowspan="4" |CPU.SAI1_TXFS
| rowspan="4" |H4
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_TX_SYNC
|-
|ALT1
|SAI5_TX_SYNC
|-
|ALT4
|CORESIGHT_EVENTO
|-
|ALT5
|GPIO4_IO10
|-
| rowspan="4" |J4.16
| rowspan="4" |SAI1_TXC
| rowspan="4" |CPU.SAI1_TXC
| rowspan="4" |J5
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_TX_BCLK
|-
|ALT1
|SAI5_TX_BCLK
|-
|ALT4
|CORESIGHT_EVENTI
|-
|ALT5
|GPIO4_IO11
|-
| rowspan="5" |J4.17
| rowspan="5" |SAI1_TXD0
| rowspan="5" |CPU.SAI1_TXD0
| rowspan="5" |F2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA0
|-
|ALT1
|SAI5_TX_DATA0
|-
|ALT4
|CORESIGHT_TRACE8
|-
|ALT5
|GPIO4_IO12
|-
|ALT6
|SRC_BOOT_CFG8
|-
| rowspan="5" |J4.18
| rowspan="5" |SAI1_TXD1
| rowspan="5" |CPU.SAI1_TXD1
| rowspan="5" |E2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA1
|-
|ALT1
|SAI5_TX_DATA1
|-
|ALT4
|CORESIGHT_TRACE9
|-
|ALT5
|GPIO4_IO13
|-
|ALT6
|SRC_BOOT_CFG9
|-
| rowspan="5" |J4.19
| rowspan="5" |SAI1_TXD2
| rowspan="5" |CPU.SAI1_TXD2
| rowspan="5" |B2
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA2
|-
|ALT1
|SAI5_TX_DATA2
|-
|ALT4
|CORESIGHT_TRACE10
|-
|ALT5
|GPIO4_IO14
|-
|ALT6
|SRC_BOOT_CFG10
|-
| rowspan="5" |J4.20
| rowspan="5" |SAI1_TXD3
| rowspan="5" |CPU.SAI1_TXD3
| rowspan="5" |D1
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA3
|-
|ALT1
|SAI5_TX_DATA3
|-
|ALT4
|CORESIGHT_TRACE11
|-
|ALT5
|GPIO4_IO15
|-
|ALT6
|SRC_BOOT_CFG11
|-
| rowspan="6" |J4.21
| rowspan="6" |SAI1_TXD4
| rowspan="6" |CPU.SAI1_TXD4
| rowspan="6" |D2
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA4
|-
|ALT1
|SAI6_RX_BCLK
|-
|ALT2
|SAI6_TX_BCLK
|-
|ALT4
|CORESIGHT_TRACE12
|-
|ALT5
|GPIO4_IO16
|-
|ALT6
|SRC_BOOT_CFG12
|-
| rowspan="6" |J4.22
| rowspan="6" |SAI1_TXD5
| rowspan="6" |CPU.SAI1_TXD5
| rowspan="6" |C2
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA5
|-
|ALT1
|SAI6_RX_DATA0
|-
|ALT2
|SAI6_TX_DATA0
|-
|ALT4
|CORESIGHT_TRACE13
|-
|ALT5
|GPIO4_IO17
|-
|ALT6
|SRC_BOOT_CFG13
|-
| rowspan="6" |J4.23
| rowspan="6" |SAI1_TXD6
| rowspan="6" |CPU.SAI1_TXD6
| rowspan="6" |B3
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA6
|-
|ALT1
|SAI6_RX_SYNC
|-
|ALT2
|SAI6_TX_SYNC
|-
|ALT4
|CORESIGHT_TRACE14
|-
|ALT5
|GPIO4_IO18
|-
|ALT6
|SRC_BOOT_CFG14
|-
| rowspan="5" |J4.24
| rowspan="5" |SAI1_TXD7
| rowspan="5" |CPU.SAI1_TXD7
| rowspan="5" |C1
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT config
Could be pulled-up or down during bootstrap.
|ALT0
|SAI1_TX_DATA7
|-
|ALT1
|SAI6_MCLK
|-
|ALT4
|CORESIGHT_TRACE15
|-
|ALT5
|GPIO4_IO19
|-
|ALT6
|SRC_BOOT_CFG15
|-
|J4.25
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|}
 
==ONE PIECE J5 pins declaration ==
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" | Voltage domain
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
! colspan="2" |Alternative Functions
|-
|J5.1
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.2
|PCIE2_RXN
|CPU.PCIE2_RXN_N
|D24
| -
|D
|
|
|
|-
|J5.3
|PCIE2_RXP
|CPU.PCIE2_RXN_P
|D25
| -
|D
|
|
|
|-
|J5.4
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.5
|PCIE2_TXN
|CPU.PCIE2_TXN_N
|E24
| -
|D
|
|
|
|-
|J5.6
|PCIE2_TXP
|CPU.PCIE2_TXN_P
|E25
| -
|D
|
|
|
|-
|J5.7
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.8
|PCIE2_REF_CLKN
|CPU.PCIE2_REF_PAD_CLK_N
|F24
| -
|D
|
|
|
|-
|J5.9
|PCIE2_REF_CLKP
|CPU.PCIE2_REF_PAD_CLK_P
|F25
| -
|D
|
|
|
|-
|J5.10
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.11
|CSI_P2_CKN
|CPU.MIPI_CSI2_CLK_N
|A19
| -
|D
|
|
|
|-
|J5.12
|CSI_P2_CKP
|CPU.MIPI_CSI2_CLK_P
|B19
| -
|D
|
|
|
|-
|J5.13
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.14
|CSI_P2_DN0
|CPU.MIPI_CSI2_D0_N
|C20
| -
|D
|
|
|
|-
|J5.15
|CSI_P2_DP0
|CPU.MIPI_CSI2_D0_P
|D10
| -
|D
|
|
|
|-
|J5.16
|CSI_P2_DN1
|CPU.MIPI_CSI2_D1_N
|A20
| -
|D
|
|
|
|-
|J5.17
|CSI_P2_DP1
|CPU.MIPI_CSI2_D1_P
|B20
| -
|D
|
|
|
|-
|J5.18
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
|J5.19
|CSI_P2_DN2
|CPU.MIPI_CSI2_D2_N
|A21
| -
|D
|
|
|
|-
|J5.20
|CSI_P2_DP2
|CPU.MIPI_CSI2_D2_P
|B21
| -
|D
|
|
|
|-
|J5.21
|CSI_P2_DN3
|CPU.MIPI_CSI2_D3_N
|C19
| -
|D
|
|
|
|-
|J5.22
|CSI_P2_DP3
|CPU.MIPI_CSI2_D3_P
|D19
| -
|D
|
|
|
|-
|J5.23
|DGND
|DGND
| -
|<nowiki>-</nowiki>
|G
|
|
|
|-
| rowspan="4" |J5.24
| rowspan="4" |I2C4_SCL
| rowspan="4" |CPU.I2C4_SCL
| rowspan="4" |F8
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|I2C4_SCL
|-
|ALT1
|PWM2_OUT
|-
|ALT2
|PCIE1_CLKREQ_B
|-
|ALT5
|GPIO5_IO20
|-
| rowspan="4" |J5.25
| rowspan="4" |I2C4_SDA
| rowspan="4" |CPU.I2C4_SDA
| rowspan="4" |F9
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|I2C4_SDA
|-
|ALT1
|PWM1_OUT
|-
|ALT2
|PCIE2_CLKREQ_B
|-
|ALT5
|GPIO5_IO21
|}
U0007
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