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MITO 8M SOM/MITO 8M Hardware/General Information/Processor and memory subsystem

1,007 bytes removed, 17:46, 28 December 2023
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! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
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! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Sep 2020/09/29
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
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<section end=History/>
<section begin=Body/>
 
''TBD: nella pagina vanno documentate le varie sezioni e documentate ad hoc a seconda del SoC (ad esempio per Bora va aggiunta la sezione PL)''
== Processor and memory subsystem ==
{| class="wikitable" |
| align="center" style="background:#f0f0f0;" |'''Processor'''
| align="center" style="background:#f0f0f0;" |'''# Coresi.MX8M Dual'''| align="center" style="background:#f0f0f0;" |'''Clocki.MX8M Quad'''| align="center" style="background:-|#f0f0f0;" Cores|2x Arm® Cortex®-A53 1x Arm® Cortex®-M4|'''L2'''4x Arm® Cortex®-A53 1x Arm® Cortex®-M4'''Cache'''|-| alignClock|| colspan="center" style="background:#f0f0f0;2" |'''LPDDR4'''1.3 GHz 1.5 GHz|-|L2 Cache| align="center" stylecolspan="background:#f0f0f0;2" |'''GPU'''1 MB| align="center" style="background:#f0f0f0;" -|'''VPU'''LPDDR4| align="center" stylecolspan="background:#f0f0f0;2" |'''Display'''32 bit @ 1600 MHz '''Controller'''(LPDDR4-3200)|VideoOutput-|'''Camera'''InputGPU| align="center" stylecolspan="background:#f0f0f0;2" |'''PCIe'''4 Shader OpenGL ES 1.1, 2.0, 3.0, 3.1Open CL 1.2Vulkan
|-
| i.MX8M Dual || 2 x Arm® Cortex®-A53 1 x Arm® Cortex®-M4 | rowspan="2" |1.3 GHz1.5 GHz VPU| rowspan="2" |1 MB || rowspan="2" |32 bit @ 1600 MHz(LPDDR4-3200) | rowspan="2" |4 Shader* OpenGL ES 1.1, 2.0, 3.0, 3.1* Open CL 1.2* Vulkan| rowspancolspan="2" |4Kp60 HEVC/H.265 main, and main 10 decoder 
4Kp60 VP9 decoder
1080p60 MPEG-2, MPEG-4p2, VC-1, VP8, RV9, AVS, MJPEG, H.263 decoder
|-|Display Controller| rowspancolspan="2" |Dual Independent
Display Support
 up tp 4kp60 | rowspan-|Video Output| colspan="2" |1 x 1x HDMI 2.0a1 x 1x MIPI-DSI 
(with MIPI to LVDS bridge)
| rowspan-|Camera Input| colspan="2" |2 x 2x MIPI CSI
(4-lanes each)
| rowspan-|PCIe| colspan="2" | 2 x 2x PCIe 2.0
(1-lane each)
|-
| i.MX8M Quad USB|colspan="2" | 4 x Arm® Cortex®-A53 2x USB 3.0 1 x Arm® Cortex®-M4 Dual role
|-
|+ align="bottom" style="caption-side: bottom" | Table: i.MX8M models comparison
=== RAM memory bank ===
DDR3 LPDD4 SDRAM memory bank is composed by 4x 161x 32-bit width chips resulting in a 64-bit combined width bankchip. The following table reports the SDRAM specifications:
{| class="wikitable" |
|-
| '''CPU connection'''||Multi-mode DDR controller (MMDC)
|-
| '''Size min'''||512 MB
|-
| '''Size max'''||4 GB
|-
| '''Width'''||64 32 bit
|-
| '''Speed'''||533 1600 MHz
|-
|}
=== NOR eMMC flash bank ===
NOR flash is a Serial Peripheral Interface (SPI) device. This device On board main storage memory eMMC is connected to the eCSPI channel 5 SDIO1 interface and by default it acts can act as boot memoryperipheral. The following table reports the NOR eMMC flash specifications:
{| class="wikitable" |
|-
| '''CPU connection'''||eCSPI channel 5SDIO1
|-
| '''Size min'''||8 MB 4 GB
|-
| '''Size max'''||64 MB |-| '''Chip select'''||ECSPI5_SS0GB
|-
| '''Bootable'''||Yes
=== NAND flash bank ===
{| style="color:#000000; border:solid 2px #73B2C7; background-color:#ededed;font-size:95%; vertical-align:middle;"
| [[File:TBD.png|30px]]
| '''Section not completed yet'''
|}
On board Alternative option for main storage memory is can be a 8-bit wide NAND flash connected to the CPU's Raw NAND flash controller. Optionally, it It can act as boot peripheral. The following table reports the NAND flash specifications:
{| class="wikitable" |
| '''CPU connection'''||Raw NAND flash controller
|-
| '''Page size'''|| 512 byte, 2 kbyte or 4 kbyteTBD
|-
| '''Size min'''||128 MB TBD
|-
| '''Size max'''||2 GB TBD
|-
| '''Width'''||8 bit
|-
| '''Chip select'''||NANDF_CS0|-| '''Bootable'''||Yes |-|} === eMMC flash bank === {| class="wikitable" | |-| '''CPU connection'''|| SDIO|-| '''Page size'''|| xxxxxx |-| '''Size min'''||xxx MB |-| '''Size max'''||xxx GB |-| '''Width'''|| xx bit |-| '''SDHC'''||TBD
|-
| '''Bootable'''||Yes
=== Memory map ===
For detailed information, please refer to chapter 2 “Memory Maps” of the [https://www.nxp.com/webapp/Download?colCode=IMX8MDQLQRM i.MX MX8M Applications Processor Reference Manual.]
=== Power supply unit ===
MITO 8M embeds all the elements required for powering the unit, therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from carrier board, and therefore users should be aware of the ranges power supply can assume as well as all other parameters.
 
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[[Category:MITO 8M]]
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