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MITO 8M SOM/MITO 8M Hardware/General Information/Processor and memory subsystem

1,763 bytes removed, 17:46, 28 December 2023
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<section begin=History/>
{| style="border-collapse:collapse; "
!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History
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!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Version!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes
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|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|X.Y.Z2020/09/29|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Month Year|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|TBD|-|-|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|[TBD_link X.Y.Z]|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Month Year|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|TBD|-|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|...|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|...|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|...First release
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|}
<section end=History/>
<section begin=Body/>
 
''TBD: nella pagina vanno documentate le varie sezioni e documentate ad hoc a seconda del SoC (ad esempio per Bora va aggiunta la sezione PL)''
== Processor and memory subsystem ==
The heart of MITO 8M module is composed by the following components:
* ''TBD: SOC name'' i.MX8M SoC application processor
* Power supply unit
* DDR LPDDR4 memory banksbank* NOR and eMMC or NAND flash banks* ''TBDConnectors: SOM connector type'' ** 1 x 204 pins SO-DIMM edge connector with interfaces signals*** partially compatible with [[AXEL Lite SOM]]** 2 x 25 pins One Piece mating board layout Expansion
This chapter shortly describes the main Axel Lite MITO 8M components.
=== Processor Info ===
{| class="wikitable" |
| align="center" style="background:#f0f0f0;"|'''Processor'''| align="center" style="background:#f0f0f0;"|'''# Cores'''| align="center" style="background:#f0f0f0;"|'''Clock'''| align="center" style="background:#f0f0f0;"|'''L2 Cache'''| align="center" style="background:#f0f0f0;"|'''DDR3'''| align="center" style="background:#f0f0f0;"|'''Graphics Acceleration'''| align="center" style="background:#f0f0f0;"|'''IPU'''| align="center" style="background:#f0f0f0;"|'''VPUi.MX8M Dual'''| align="center" style="background:#f0f0f0;"|'''SATA-IIi.MX8M Quad'''
|-
| i.MX6 Solo || 1 ||800 MHz<br>1 GHz ||512 KB ||32 bit @ 400 MHz ||3D: Vivante GC880<br>2D: Vivante GC320<br>Vector: N.A. |# Cores|2x Arm® Cortex®-A53 1x Arm® Cortex®-M4||4x Arm® Cortex®-A53 1x ||N.A.Arm® Cortex®-M4
|-
| i.MX6 Dual Clock|| colspan="2 " ||850 MHz<br>1 .3 GHz<br>1.2 5 GHz ||1 MB ||64 bit @ 533 MHz ||3D: Vivante GC2000<br>2D: Vivante GC320<br>Vector: Vivante GC335 ||2x ||2x || Yes
|-
| i.MX6 Quad L2 Cache|| 4 ||850 MHz<br>1 GHz<br>1.colspan="2 GHz |" |1 MB ||64 bit @ 533 MHz ||3D: Vivante GC2000<br>2D: Vivante GC320<br>Vector: Vivante GC335 ||2x ||2x || Yes
|-
|+ alignLPDDR4| colspan="bottom2" style|32 bit @ 1600 MHz (LPDDR4-3200)|-|GPU| colspan="caption-side: bottom2" | Table: i4 Shader OpenGL ES 1.1, 2.0, 3.MX6 models comparison0, 3.1Open CL 1.2Vulkan|}-|VPU| colspan=== RAM memory bank ==="2" |4Kp60 HEVC/H.265 main, and main 10 decoder 4Kp60 VP9 decoder
DDR3 SDRAM memory bank is composed by 4x 16-bit width chips resulting in a 64-bit combined width bank4Kp30 AVC/H. The following table reports the SDRAM specifications:264 decoder
{| class="wikitable" | 1080p60 MPEG-2, MPEG-4p2, VC-1, VP8, RV9, AVS, MJPEG, H.263 decoder
|-
| '''CPU connection'''Display Controller|colspan="2" |Multi-mode DDR controller (MMDC)Dual Independent Display Supportup tp 4kp60
|-
| '''Size min'''Video Output|colspan="2" |512 MB 1x HDMI 2.0a 1x MIPI-DSI(with MIPI to LVDS bridge)
|-
| '''Size max'''Camera Input|colspan="2" |2x MIPI CSI (4 GB -lanes each)
|-
| '''Width'''PCIe|colspan="2" |64 bit 2x PCIe 2.0 (1-lane each)
|-
| '''Speed'''USB|colspan="2" |533 MHz 2x USB 3.0 Dual role
|-
|+ align="bottom" style="caption-side: bottom" | Table: i.MX8M models comparison
|}
=== NOR flash RAM memory bank ===
NOR flash LPDD4 SDRAM memory bank is a Serial Peripheral Interface (SPI) device. This device is connected to the eCSPI channel 5 and composed by default it acts as boot memory1x 32-bit width chip. The following table reports the NOR flash SDRAM specifications:
{| class="wikitable" |
|-
| '''CPU connection'''||eCSPI channel 5Multi-mode DDR controller (MMDC)
|-
| '''Size min'''||8 MB |-| '''Size max'''||64 MB 4 GB
|-
| '''Chip selectWidth'''||ECSPI5_SS032 bit
|-
| '''BootableSpeed'''||Yes1600 MHz
|-
|}
=== NAND eMMC flash bank ===
On board main storage memory eMMC is a 8-bit wide NAND flash connected to the CPU's Raw NAND flash controller. Optionally, SDIO1 interface and it can act as boot peripheral. The following table reports the NAND eMMC flash specifications:
{| class="wikitable" |
|-
| '''CPU connection'''||Raw NAND flash controllerSDIO1
|-
| '''Page sizeSize min'''|| 512 byte, 2 kbyte or 4 kbyteGB
|-
| '''Size minmax'''||128 MB 64 GB
|-
| '''Size max'''||2 GB |-| '''Width'''||8 bit |-| '''Chip select'''||NANDF_CS0|-| '''Bootable'''||Yes
|-
|}
=== eMMC NAND flash bank ==={| style="color:#000000; border:solid 2px #73B2C7; background-color:#ededed;font-size:95%; vertical-align:middle;"| [[File:TBD.png|30px]]| '''Section not completed yet'''|} 
Alternative option for main storage memory can be a 8-bit wide NAND flash connected to the CPU's Raw NAND flash controller. It can act as boot peripheral. The following table reports the NAND flash specifications:
{| class="wikitable" |
|-
| '''CPU connection'''|| SDIORaw NAND flash controller
|-
| '''Page size'''|| xxxxxx TBD
|-
| '''Size min'''||xxx MB TBD
|-
| '''Size max'''||xxx GB TBD
|-
| '''Width'''|| xx 8 bit
|-
| '''SDHCChip select'''||TBD
|-
| '''Bootable'''||Yes
|-
|}
 
=== Memory map ===
For detailed information, please refer to chapter 2 “Memory Maps” of the [https://www.nxp.com/webapp/Download?colCode=IMX8MDQLQRM i.MX MX8M Applications Processor Reference Manual.]
=== Power supply unit ===
MITO 8M embeds all the elements required for powering the unit, therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from carrier board, and therefore users should be aware of the ranges power supply can assume as well as all other parameters.
 
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[[Category:MITO 8M]]
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