ZERO SOM/ZERO Evaluation Kit/Interfaces and Connectors/JTAG
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Contents
JTAG interface[edit | edit source]
JTAG interface allow the developer to access every peripheral of the SoC using a debugger.
Description[edit | edit source]
The JTAG interface available on the Evaluation Kit at the connector J55.
J55 is a Samtec .050"x.050 terminale strip header connector (FTSH-110-01-L-DV-007).
Signals[edit | edit source]
The following table describes the interface signals:
| Pin# | Pin name | Function | ARM-20 JTAG | Notes |
|---|---|---|---|---|
| 1 | VREF | - | 1 | 1V8 |
| 2 | JTAG_TMS | - | 7 | - |
| 4 | JTAG_TCK | - | 9 | - |
| 6 | JTAG_TDO | - | 13 | - |
| 8 | JTAG_TDI | - | 5 | - |
| 10 | JTAG_TRST | - | 15 | - |
| 12 | JTAG_RTCK | - | 11 | |
| 14,18,20 | N.C. | - | ||
| 3,5,9,11,13,15,17,19 | DGND | - | 4,6,8,10,12,14,16,18,20 | For example documented on Lauterbach specification |
(*) optional signals, keep the possibility to be unconnected.
