a000298_approval, dave_user
549
edits
Changes
→SoM's signals mapping: update bank 13
==SoM's signals mapping==
===Bora Lite===
As known, Bora Lite requires an [[BoraLite_Adapter_for_the_BoraXEVB_carrier_board|adapter]] to be mounted on the BoraXEVB carrier board. The adapter swap some signals to allow to use some carrier board peripherals routed on unavailable pins of the SoM. For this reason, it can be tricky to find out where the SoM's signals are routed at the carrier board level. The following table details such routingfor PL banks. Here it is assumed to use an adapter with default mounting options.
{| class="wikitable"
|JP17.3
|PMOD [A]
|IO_L11P_T1_SRCC_13|J26.12|LVDS
|-
|IO_L11N_T1_SRCC_13
|JP17.4
|PMOD [A]
|IO_L11N_T1_SRCC_13|J26.11|LVDS
|-
|IO_L12P_T1_MRCC_13
|JP17.2
|PMOD [A]
|IO_L12P_T1_MRCC_13IO_L9P_T1_DQS_13|J26J30.61|LVDSONE PIECE
|-
|IO_L12N_T1_MRCC_13
|JP17.1
|PMOD [A]
|IO_L12N_T1_MRCC_13IO_L9N_T1_DQS_13|J26J30.53|LVDSONE PIECE
|-
|IO_L13P_T2_MRCC_13
|JP17.7
|PMOD [A]
|IO_L13P_T2_MRCC_13IO_L7P_T1_13|J26J30.1524|LVDSONE PIECE
|-
|IO_L13N_T2_MRCC_13
|JP17.8
|PMOD [A]
|IO_L13N_T2_MRCC_13IO_L7N_T1_13|J26J30.1426|LVDSONE PIECE
|-
|IO_L14P_T2_SRCC_13
|n/a
|ETH1_RXCK
| colspan="3" IO_L15P_T2_DQS_13|n/aJ30.25|ONE PIECE
|-
|IO_L14N_T2_SRCC_13
|n/a
|ETH1_RXCTL
| colspan="3" IO_L15N_T2_DQS_13|n/aJ30.27|ONE PIECE
|-
|IO_L15P_T2_DQS_13
|JP17.6
|PMOD [A]
|IO_L14P_T2_SRCC_13IO_L5P_T0_13|J26J30.920|LVDSONE PIECE
|-
|IO_L15N_T2_DQS_13
|JP17.5
|PMOD [A]
|IO_L14N_T2_SRCC_13IO_L5N_T0_13|J26J30.818|LVDSONE PIECE
|-
|IO_L16N_T2_13
|IO_L16N_T2_13
|R235.1n/a|ETH1_TXCTL
|IO_L16N_T2_13
|RP79J30.831|ONE PIECE
|-
|IO_L16P_T2_13
|IO_L16P_T2_13|n/a|ETH1_TXCK|IO_L16P_T2_13|J30.29|ONE PIECE
|-
|IO_L17N_T2_13
|IO_L17N_T2_13|n/a|ETH1_RXD1|IO_L17N_T2_13|J30.35|ONE PIECE
|-
|IO_L17P_T2_13
|IO_L17P_T2_13|n/a|ETH1_RXD0|IO_L17P_T2_13|J30.33|ONE PIECE
|-
|IO_L18N_T2_13
|IO_L18N_T2_13|n/a|ETH1_RXD3|IO_L18N_T2_13|J30.39|ONE PIECE
|-
|IO_L18P_T2_13
|IO_L18P_T2_13|n/a|ETH1_RXD2|IO_L18P_T2_13|J30.37|ONE PIECE
|-
|IO_L19N_T3_VREF_13
|IO_L19N_T3_VREF_13|n/a|ETH1_TXD1|IO_L19N_T3_VREF_13|J30.43|ONE PIECE
|-
|IO_L19P_T3_13
|IO_L19P_T3_13|n/a|ETH1_TXD0|IO_L19P_T3_13|J30.41|ONE PIECE
|-
|IO_L20N_T3_13
|IO_L20N_T3_13|n/a|ETH1_TXD3|IO_L20N_T3_13|J30.47|ONE PIECE
|-
|IO_L20P_T3_13
|IO_L20P_T3_13|n/a|ETH1_TXD2|IO_L20P_T3_13|J30.45|ONE PIECE
|-
|IO_L21N_T3_DQS_13
|IO_L21N_T3_DQS_13|n/a|ETH1_MDC|IO_L21N_T3_DQS_13|J30.51|ONE PIECE
|-
|IO_L21P_T3_DQS_13
|IO_L21P_T3_DQS_13|n/a|ETH1_MDIO|IO_L21P_T3_DQS_13|J30.49|ONE PIECE
|-
|IO_L22N_T3_13
|IO_L22N_T3_13
|
|
|IO_L22N_T3_13|J30.55||ONE PIECE
|-
|IO_L22P_T3_13
|IO_L22P_T3_13|n/a|DWM_WIFI_IRQ|IO_L22P_T3_13|J30.53|ONE PIECE
|-
| rowspan="2" |IO_L6N_T0_VREF_13
|JP23.3
|PMOD [B]
| rowspan="2" |IO_0_13IO_L6N_T0_VREF_13| rowspan="2" |J26J30.1730| rowspan="2" |LVDSONE PIECE
|-
|n/a
