10
edits
Changes
Update SO-DIMM connector - J1 pinout
| 2||AM335X_GPMC_WPn||CPU.[GPMC_WPN/GMII2_RXERR/GPMC_CSN5/RMII2_RXERR/MMC2_SDCD/PR1_MII1_TXEN/UART4_TXD/GPIO0_31]||U17||VAUX2
|IO
|||HW option: Optionally, this pin can connected to the WP NAND flash
|-
| 3||AM335X_I2C0_SCL||CPU.[I2C0_SCL/TIMER7/UART2_RTSN/ECAP1_IN_PWM1_OUT////GPIO3_6]||C16||VAUX2
|IO||10kΩ ↑
|Internally connected to a 10K pull-up resistor the PMIC and EEPROM
|-
| 4||AM335X_GPMC_CS0n||CPU.[GPMC_CSN0///////GPIO1_29]||V6||VAUX2
| 5||AM335X_I2C0_SDA||CPU.[I2C0_SDA/TIMER4/UART2_CTSN/ECAP2_IN_PWM2_OUT////GPIO3_5]||C17||VAUX2
|IO||10kΩ ↑
|Internally connected to a 10K pull-up resistor the PMIC and EEPROM
|-
| 6||AM335X_GPMC_CS1n||CPU.[GPMC_CSN1/GPMC_CLK/MMC1_CLK/PR1_EDIO_DATA_IN6/PR1_EDIO_DATA_OUT6/PR1_PRU1_PRU_R30_12/PR1_PRU1_PRU_R31_12/GPIO1_30]||U9||VAUX2
|-
| 7||WD_SET0||||||3.3V||I||10kΩ ↓
|HW option: mount Optionally, this pin can be pullup
|-
| 8||AM335X_GPMC_CS2n||CPU.[GPMC_CSN2/GPMC_BE1N/MMC1_CMD/PR1_EDIO_DATA_IN7/PR1_EDIO_DATA_OUT7/PR1_PRU1_PRU_R30_13/PR1_PRU1_PRU_R31_13/GPIO1_31]||V9||VAUX2||IO||||
|-
| 9||WD_SET1||||||3.3V||I||10kΩ ↑||HW option: mount Optionally, this pin can be pulldown
|-
| 10||AM335X_GPMC_CS3n||CPU.[GPMC_CSN3///MMC2_CMD/PR1_MII0_CRS/PR1_MDIO_DATA/EMU4/GPIO2_0]||T13||VAUX2||IO||||
|-
| 11||WD_SET2||||||3.3V||I||10kΩ ↑||HW option: mount Optionally, this pin can be pulldown
|-
| 12||DGND||||||||G
|||
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| 13||EEPROM_WP||||||3.3V||I||10kΩ ↓||HW option: mount Optionally, this pin can be pullup
|-
| 14||AM335X_GPMC_CLK||CPU.[GPMC_CLK/LCD_MEMORY_CLK/GPMC_WAIT1/MMC2_CLK/PR1_MII1_CRS/PR1_MDIO_MDCLK/MCASP0_FSR/GPIO2_1]||V12||VAUX2||IO||||
|-
| 15||EEPROM_A1||||||3.3V||I||10kΩ ↓||HW option: mount Optionally, this pin can be pullup
|-
| 16||AM335X_GPMC_WEn||CPU.[GPMC_WEN//TIMER6/////GPIO2_4]||U6||VAUX2||IO||||Internally connected to the NAND flash (if present)
|-
| 17||EEPROM_A0||||||3.3V||I||10kΩ ↓||HW option: mount Optionally, this pin can be pullup
|-
| 18||AM335X_GPMC_OEn_REn||CPU.[GPMC_OEN_REN//TIMER6/////GPIO2_4]||T7||VAUX2||IO||||Internally connected to the NAND flash (if present)
| 50||AM335X_GPMC_A10||CPU.[GPMC_A10/GMII2_RXD1/RGMII2_RD1/RMII2_RXD1/GPMC_A26/PR1_MII1_RXDV/MCASP0_AXR0/GPIO1_26]||T16||VAUX2||IO||||
|-
| 51||AM335X_SPI0_CS1||CPU.[SPI0_CS1/UART3_RXD/ECAP1_IN_PWM1_OUT/MMC0_POW/XDMA_EVENT_INTR2/MMC0_SDCD/EMU4/GPIO0_6]||C15||VAUX2||IO||||HW option: Optionally, this pin can connected to the RFU NOR flash
|-
| 52||DGND||||||||G
| 153||EMAC0_PHY_LED_SPEED||ETHPHY.LED2/nINTSEL||2||3.3V||O||10kΩ ↓||10kOhm pull-down
|-
| 154||NC/OUT_PMIC_VRTCMonitoringPMIC_VRTC//OUT_VDD3_SMPSVDD3_SMPS//OUT_VDIG1|VDIG1|||||||SO||||By default, this pin must not be connected. Optionally, it can route power voltages generated by Diva PSU. This option is meant to allow monitoring of such voltages by carrier board circuitry. It is not meant to power carrier board devices. As these options requires custom manufacturing BOMs, please contact the [mailto:sales@dave.eu Sales Department] for more information.
|-
| 155||EMAC0_PHY_LED_LINK/ACT||ETHPHY.LED1/nREGOFF||3||3.3V||O||10kΩ ↓||10kOhm pull-down
|-
| 156||NC/Monitoring|VRTC_LDO|||||||SO||||By default, this pin must not be connected. Optionally, it can route power voltages generated by Diva PSU. This option is meant to allow monitoring of such voltages by carrier board circuitry. It is not meant to power carrier board devices. As these options requires custom manufacturing BOMs, please contact the [mailto:sales@dave.eu Sales Department] for more information.
|-
| 157||AM335X_GMII1_TXD3||CPU.[GMII1_TXD3/DCAN0_TX/RGMII1_TD3/UART4_RXD/MCASP1_FSX/MMC2_DAT1/MCASP0_FSR/GPIO0_16]||J18||VAUX2||IO||||
|-
| 158||NC/Monitoring|VDAC|||||||SO||||By default, this pin must not be connected. Optionally, it can route power voltages generated by Diva PSU. This option is meant to allow monitoring of such voltages by carrier board circuitry. It is not meant to power carrier board devices. As these options requires custom manufacturing BOMs, please contact the [mailto:sales@dave.eu Sales Department] for more information.
|-
| 159||NC/AM335X_GMII1_TXD2||CPU.[GMII1_TXD2/DCAN0_RX/RGMII1_TD2/UART4_TXD/MCASP1_AXR0/MMC2_DAT2/MCASP0_AHCLKX/GPIO0_17]||K15||VAUX2||IO||||Internally connected to the WDT (if present) – HW option. This pin is not connected in some models, please contact the Sales Department for more information.
|-
| 160||NC/Monitoring|VPLL|||||||SO||||By default, this pin must not be connected. Optionally, it can route power voltages generated by Diva PSU. This option is meant to allow monitoring of such voltages by carrier board circuitry. It is not meant to power carrier board devices. As these options requires custom manufacturing BOMs, please contact the [mailto:sales@dave.eu Sales Department] for more information.
|-
| 161||DGND||||||||G
|||
|-
| 162||NC/Monitoring|VAUX1|||||||SO||||By default, this pin must not be connected. Optionally, it can route power voltages generated by Diva PSU. This option is meant to allow monitoring of such voltages by carrier board circuitry. It is not meant to power carrier board devices. As these options requires custom manufacturing BOMs, please contact the [mailto:sales@dave.eu Sales Department] for more information.
|-
| 163||AM335X_GMII1_RXDV||CPU.[GMII1_RXDV/LCD_MEMORY_CLK/RGMII1_RCTL/UART5_TXD/MCASP1_ACLKX/MMC2_DAT0/MCASP0_ACLKR/GPIO3_4]||J17||VAUX2||IO||||
|-
| 164||NC/Monitoring|VAUX2|||||||SO||||By default, this pin must not be connected. Optionally, it can route power voltages generated by Diva PSU. This option is meant to allow monitoring of such voltages by carrier board circuitry. It is not meant to power carrier board devices. As these options requires custom manufacturing BOMs, please contact the [mailto:sales@dave.eu Sales Department] for more information.
|-
| 165||AM335X_GMII1_MDIO_CLK||CPU.[MDIO_CLK/TIMER5/UART5_TXD/UART3_RTSN/MMC0_SDWP/MMC1_CLK/MMC2_CLK/GPIO0_1]||M18||VAUX2||IO||||Internally connected to the ETH PHY
|-
| 166||NC/Monitoring|VDD1_SMPS|||||||SO||||By default, this pin must not be connected. Optionally, it can route power voltages generated by Diva PSU. This option is meant to allow monitoring of such voltages by carrier board circuitry. It is not meant to power carrier board devices. As these options requires custom manufacturing BOMs, please contact the [mailto:sales@dave.eu Sales Department] for more information.
|-
| 167||AM335X_GMII1_MDIO_DATA||CPU.[MDIO_DATA/TIMER6/UART5_RXD/UART3_CTSN/MMC0_SDCD/MMC1_CMD/MMC2_CMD/GPIO0_0]||M17||VAUX2||IO||1.5kΩ ↑||Internally connected to the ETH PHY
|-
| 168||NC/Monitoring|VDD2_SMPS|||||||SO||||By default, this pin must not be connected. Optionally, it can route power voltages generated by Diva PSU. This option is meant to allow monitoring of such voltages by carrier board circuitry. It is not meant to power carrier board devices. As these options requires custom manufacturing BOMs, please contact the [mailto:sales@dave.eu Sales Department] for more information.
|-
| 169||AM335X_GMII1_COL||CPU.[GMII1_COL/RMII2_REFCLK/SPI1_SCLK/UART5_RXD/MCASP1_AXR2/MMC2_DAT3/MCASP0_AXR2/GPIO3_0]||H16||VAUX2||IO||||Internally used for DDR power management (if required) – HW option
| 175||AM335X_GMII1_RXCLK||CPU.[GMII1_RXCLK/UART2_TXD/RGMII1_RCLK/MMC0_DAT6/MMC1_DAT1/UART1_DSRN/MCASP0_FSX/GPIO3_10]||L18||VAUX2||IO||||
|-
| 176||NC/Monitoring|VDIG2|||||||SO||||By default, this pin must not be connected. Optionally, it can route power voltages generated by Diva PSU. This option is meant to allow monitoring of such voltages by carrier board circuitry. It is not meant to power carrier board devices. As these options requires custom manufacturing BOMs, please contact the [mailto:sales@dave.eu Sales Department] for more information.
|-
| 177||AM335X_GMII1_TXCLK||CPU.[GMII1_TXCLK/UART2_RXD/RGMII1_TCLK/MMC0_DAT7/MMC1_DAT0/UART1_DCDN/MCASP0_ACLKX/GPIO3_9]||K18||VAUX2||IO||||
|-
| 178||NC/Monitoring|DDR_VDDS|||||||SO||||By default, this pin must not be connected. Optionally, it can route power voltages generated by Diva PSU. This option is meant to allow monitoring of such voltages by carrier board circuitry. It is not meant to power carrier board devices. As these options requires custom manufacturing BOMs, please contact the [mailto:sales@dave.eu Sales Department] for more information.
|-
| 179||PMIC_CLK32OUT||PMIC.CLK32KOUT||PMIC.38||VAUX33
|||
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| 182||NC/Monitoring|VMMC|||||||SO||||By default, this pin must not be connected. Optionally, it can route power voltages generated by Diva PSU. This option is meant to allow monitoring of such voltages by carrier board circuitry. It is not meant to power carrier board devices. As these options requires custom manufacturing BOMs, please contact the [mailto:sales@dave.eu Sales Department] for more information.
|-
| 183||PMIC_PWR_EN||CPU.PMIC_PWR_EN, PMIC.PWRHOLD||CPU.C6, PMIC.1||VRTC||O||||
|-
| 184||NC/Monitoring|3.3V|||||||SO||||By default, this pin must not be connected. Optionally, it can route power voltages generated by Diva PSU. This option is meant to allow monitoring of such voltages by carrier board circuitry. It is not meant to power carrier board devices. As these options requires custom manufacturing BOMs, please contact the [mailto:sales@dave.eu Sales Department] for more information.
|-
| 185||PMIC_INT1||PMIC.INT1||PMIC.45||VAUX33
|O||||
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| 186||VIN||||||||S||||
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| 187||PMIC_SLEEP||PMIC.SLEEP||PMIC.37||VAUX33
|I||||
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| 188||VIN||||||||S||||
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| 189||PMIC_PWRON||PMIC.PWRON|||PMIC.33|VIN||I||10kΩ ↑||
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| 190||VIN||||||||S||||
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| 191||PMIC_nRESPWRON||PMIC.nRESPWRON|||PMIC.40|VAUX33
|O||10kΩ ↓||
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|||
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| 193||MRSTn||||||3.3V||I||10kΩ ↑||Internally connected to PORSTn with logic port
|-
| 194||VIN||||||||S||||
|-
| 195||RTC_PWRONRSTn||CPU.RTC_PWRONRSTn||B5||VRTC||I||100kΩ ↓||Internally connected to VRTC with logic port
|-
| 196||VIN||||||||S||||
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| 197||WARMRSTn||CPU.WARMRSTn|||A10|VAUX2||O||10kΩ ↑||Internally connected to NOR flash and ETH PHY
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| 198||VIN||||||||S||||
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| 199||EXT_PORSTn||||||3.3V||I||10kΩ ↑||Internally connected to PORSTn_OUT with logic port
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| 200||VIN||||||||S||||
