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| '''DAVE Embedded Systems''' Developers' Wiki||http://wiki.dave.eu/index.php/Main_Page

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== Conventions, Abbreviations, Acronyms ==

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| BTN||Button

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| CPU||"Sitara" AM335x<br>ARMv7 architecture<br>Cortex A8 @ 300/600/800/1000 ||

| Storage||Flash NOR SPI<br>Flash NAND on Local bus<br>I²C 32 kbit EEPROM||

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| Graphics Controller||Up to 24-Bits Data Output<br>Resolution Up to 2048x2048 (With Maximum 126-MHz Pixel Clock)<br>TFT/RGB support ||

| Miscellaneous||Up to 8x 12-bit ADC channels||

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| Supply Voltage||[3.6 - 5.5] V, voltage regulation on board||

| Connectors||204-pin SO-DIMM||

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CPU.<x> : pin connected to CPU pad named <x><br>

KEY.<x>: pin connected to the key switch controller<br>

MTR: pin connected to voltage monitors<br>

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| EMAC[x]||Ethernet MAC. “x” represents the port number (0 or 1)

| I2C[x]||I2C channel. “x” represents the channel number (0 to 3)

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| 8||AM335X_GPMC_CS2n||CPU.[GPMC_CSN2/GPMC_BE1N/MMC1_CMD/PR1_EDIO_DATA_IN7/PR1_EDIO_DATA_OUT7/PR1_PRU1_PRU_R30_13/PR1_PRU1_PRU_R31_13/GPIO1_31]||V9||||||||

| 11||WD_SET2||||||||||||

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| 13||EEPROM_WP||||||||||||

| 20||AM335X_GPMC_ADVn_ALE||CPU.[GPMC_ADVN_ALE//TIMER4/////GPIO2_2]||R7||||||||Internally connected to the NAND flash (if present)

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| 22||AM335X_GPMC_BE0n_CLE||CPU.[GPMC_BE0N_CLE//TIMER5/////GPIO2_5]||T6||||||||Internally connected to the NAND flash (if present)

| 31||AM335X_UART0_CTSn||CPU.[UART0_CTSN/UART4_RXD/DCAN1_TX/I2C1_SDA/SPI1_D0/TIMER7/PR1_EDC_SYNC0_OUT/GPIO1_8]||E18||||||||

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| 33||AM335X_UART1_TXD||CPU.[UART1_TXD/MMC2_SDWP/DCAN1_RX/I2C1_SCL//PR1_UART0_TXD/PR1_PRU0_PRU_R31_16/GPIO0_15]||D15||||||||

| 40||AM335X_GPMC_A5||CPU.[GPMC_A5/GMII2_TXD0/RGMII2_TD0/RMII2_TXD0/GPMC_A21/PR1_MII1_RXD3/EQEP1B_IN/GPIO1_21]||V15||||||||

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| 42||AM335X_GPMC_A6||CPU.[GPMC_A6/GMII2_TXCLK/RGMII2_TCLK/MMC2_DAT4/GPMC_A22/PR1_MII1_RXD2/EQEP1_INDEX/GPIO1_22]||U15||||||||

| 51||AM335X_SPI0_CS1||CPU.[SPI0_CS1/UART3_RXD/ECAP1_IN_PWM1_OUT/MMC0_POW/XDMA_EVENT_INTR2/MMC0_SDCD/EMU4/GPIO0_6]||C15||||||||

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| 53||USB0_CE||CPU.USB0_CE||M15||||||||

| 60||AM335X_GPMC_AD2||CPU.[GPMC_AD2/MMC1_DAT2//////GPIO1_2]||R8||||||||Internally connected to the NAND flash (if present)

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| 62||AM335X_GPMC_AD3||CPU.[GPMC_AD3/MMC1_DAT3//////GPIO1_3]||T8||||||||Internally connected to the NAND flash (if present)

| 71||AM335X_XDMA_EVENT_INTR1||CPU.[XDMA_EVENT_INTR1//TCLKIN/CLKOUT2/TIMER7/PR1_PRU0_PRU_R31_16/EMU3/GPIO0_20]||D14||||||||

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| 73||USB1_CE||CPU.USB1_CE||P18||||||||

| 80||AM335X_GPMC_AD11||CPU.[GPMC_AD11/LCD_DATA20/MMC1_DAT3/MMC2_DAT7/EHRPWM2_SYNCO/PR1_MII0_TXD3//GPIO0_27]||U12||||||||

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| 82||AM335X_GPMC_AD12||CPU.[GPMC_AD12/LCD_DATA19/MMC1_DAT4/MMC2_DAT0/EQEP2A_IN/PR1_MII0_TXD2/PR1_PRU0_PRU_R30_14/GPIO1_12]||T12||||||||

| 91||AM335X_AIN2||CPU.AIN2||B7||||||||

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| 94||AM335X_LCD_VSYNC||CPU.[LCD_VSYNC/GPMC_A8//PR1_EDIO_DATA_IN2/PR1_EDIO_DATA_OUT2/PR1_PRU1_PRU_R30_8/PR1_PRU1_PRU_R31_8/GPIO2_22]||U5||||||||

| 111||AM335X_MMC_D3||CPU.[MMC0_DAT3/GPMC_A20/UART4_CTSN/TIMER5/UART1_DCDN/PR1_PRU0_PRU_R30_8/PR1_PRU0_PRU_R31_8/GPIO2_26]||F17||||||||

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| 113||AM335X_MMC_D2||CPU.[MMC0_DAT2/GPMC_A21/UART4_RTSN/TIMER6/UART1_DSRN/PR1_PRU0_PRU_R30_9/PR1_PRU0_PRU_R31_9/GPIO2_27]||F18||||||||

| 120||AM335X_LCD_DATA9||CPU.[LCD_DATA9/GPMC_A13/EHRPWM1_SYNCO/MCASP0_FSX/UART5_RXD/PR1_MII0_RXD2/UART2_RTSN/GPIO2_15]||U2||||||||

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| 122||AM335X_LCD_DATA10||CPU.[LCD_DATA10/GPMC_A14/EHRPWM1A/MCASP0_AXR0//PR1_MII0_RXD1/UART3_CTSN/GPIO2_16]||U3||||||||

| 131||JTAG_TDI||CPU.TDI||B11||||||||

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| 133||JTAG_TMS||CPU.TMS||C11||||||||

| 140||AM335X_MCASP0_FSX||CPU.[MCASP0_FSX/EHRPWM0B//SPI1_D0/MMC1_SDCD/PR1_PRU0_PRU_R30_1/PR1_PRU0_PRU_R31_1/GPIO3_15]||B13||||||||

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| 142||AM335X_MCASP0_AXR0||CPU.[MCASP0_AXR0/EHRPWM0_TRIPZONE_INPUT//SPI1_D1/MMC2_SDCD/PR1_PRU0_PRU_R30_2/PR1_PRU0_PRU_R31_2/GPIO3_16]||D12||||||||

| 151||ETH_RX+||ETHPHY.RXP||31||||||||

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| 153||EMAC0_PHY_LED_SPEED||ETHPHY.LED2/nINTSEL||2||||||||10kOhm pull-down

| 160||NC/Monitoring||||||||||||By default, this pin must not be connected. Optionally, it can route power voltages generated by Diva PSU. This option is meant to allow monitoring of such voltages by carrier board circuitry. It is not meant to power carrier board devices. As these options requires custom manufacturing BOMs, please contact the [mailto:sales@dave.eu Sales Department] for more information.

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| 162||NC/Monitoring||||||||||||By default, this pin must not be connected. Optionally, it can route power voltages generated by Diva PSU. This option is meant to allow monitoring of such voltages by carrier board circuitry. It is not meant to power carrier board devices. As these options requires custom manufacturing BOMs, please contact the [mailto:sales@dave.eu Sales Department] for more information.

| 171||AM335X_GMII1_RXD3||CPU.[GMII1_RXD3/UART3_RXD/RGMII1_RD3/MMC0_DAT5/MMC1_DAT2/UART1_DTRN/MCASP0_AXR0/GPIO2_18]||L17||||||||

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| 173||AM335X_GMII1_RXD2||CPU.[GMII1_RXD2/UART3_TXD/RGMII1_RD2/MMC0_DAT4/MMC1_DAT3/UART1_RIN/MCASP0_AXR1/GPIO2_19]||L16||||||||

| 180||OUT_VAUX33||PMIC.VAUX33||PMIC.4||||||||This signal can be used to synchronize powering on/off of carrier board circuitry that interfaces CPU I/O directly. Please refer to section [[Hardware_Manual_(Diva)#Power_Supply_Unit_.28PSU.29_and_recommended_power-up_sequence | PSU and recommended power up sequence]].

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| 182||NC/Monitoring||||||||||||By default, this pin must not be connected. Optionally, it can route power voltages generated by Diva PSU. This option is meant to allow monitoring of such voltages by carrier board circuitry. It is not meant to power carrier board devices. As these options requires custom manufacturing BOMs, please contact the [mailto:sales@dave.eu Sales Department] for more information.

| 191||PMIC_nRESPWRON||PMIC.nRESPWRON||||||||||

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| 193||MRSTn||||||||||||

| 200||VIN||||||||||||

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| 202||VIN||||||||||||