[[File:BoraXEVB-01.png|500px|frameless|border]]
==PL's I/O voltage selections==
PL's I/O banks voltage can be selected via configuration jumpers. It is worth remembering that:
*'''each bank must be powered even if none of its I/Os is used'''
*'''voltage selection must be done before powering up the board'''.
==Block Diagram== The following table recaps the characteristics of the PL's I/O picture shows BORA Xpress EVB block diagram: [[File:Boraxevb-block_diagram.png|thumb|center|600px|BoraXEVB simplified block diagram]]===Configurable routing options===FPGA banks#12, #34 and #35 supports different routing options as shown in terms the following picture. For a detailed description of allowable power suppliesFMC connector routing, please refer to [[#FPGA Mezzanine Card (FMC) Connector - J27|this section]].[[File:Boraxevb-FPGA-signals-routing.png|thumb|center|600px|Configurable routing options diagram]] == Features ==
{|class="wikitable" style="text-align: center;"* 10/100/1000 Ethernet #0 (PS)! rowspan="2" style="text-align: center; font-weight: bold;" | Zynq p* 10/100/n1000 Ethernet #1 (Routed through EMIO)! colspan="* 1x USB 2" style="text-align: center; font-weight: bold;" | Bank #34.0 OTG (MicroAB connector)* 1x Serial port (RS232 DB9)* 1x MicroSD* 1x FPGA Mezzanine Card (FMC) Connector! colspan="2" style="text-align: center; font-weight: bold;" | Bank #13* XADC! colspan="2" style="text-align: center; font-weight: bold;" | ** Some signals of Bank #35|can be configured as XADC signals. For this reason they can be routed alternatively to 2.54mm-pitch connectors, instead of FMC connector.| style="text* State-align: center; fontof-weight: bold;" | Type [1]| style="textthe-alignart programmable MEMS clock generator (Silicon Labs Si504): center; font-weight: bold;" | Ithis is an alternative clock source to allow the user to easily experiment his/O voltage settingher own peripherals and IPs on FPGA* JTAG port* Socket for [[Wireless_Module_(DWM) | style="text-align: center; font-weight: bold;" | Type [1DWM Wireless Module]]| style="text* Digilent Pmod™ Compatible expansion connectors* Headers for external for NAND flash and SPI NOR flash* 2.54mm-align: center; fontpitch pin-weight: bold;" | I/O strip connectors for Bora Xpress PS and PL configurable peripherals (MIO and EMIO interfaces, GPIOs, custom IPs, ..)* Jumpers for voltage settingselection of the PL banks| style* +12V power connector == Known limitations =="text-align Board version CS040713A has the following limitations: center; font-weight: bold;" | Type [1] {| styleclass="text-align: center; font-weight: bold;wikitable" | I/O voltage setting
|-
| style="text-align: center;" | 7015!Issue(CLG485 package)!Description| style="text-align: center;" | HRLCD_BKLT_PWM I/O voltage(1| LCD_BKLT_PWM signal is derived from IO_0_13 on BANK13.In the case of LVDS signals for LCD the BANK 13 must be powered at 2 - 3.3V)| style="text-align: center;" | User defined| style="text-align: center;" | HR(15V.So in this case LCD_BKLT_PWM is an LVCMOS 2 - .5V signal. It is recommended to place a voltage level translator to 3.3V)if the signal voltages are not compatible with the LCD diplay backlight input.| style="text-align: center;" | User definedFMC connector| style="text-align: center;" For the [[Product_serial_number| HR(1.2 serial numbers]] included in the range EVBBX0000C0R00A0 - 3EVBBX0000C0R00AB, the connector that is actually mounted on the board is the LPC version, not the HPC version listed in the specifications.3V)| style="text-align: center;" | User defined
|-
| style="text-align: center;" | 7030
(SBG485 package)
| style="text-align: center;" | HP
(1.2 - 1.8V)
| style="text-align: center;" | User defined
| style="text-align: center;" | HR
(1.2 - 3.3V)
| style="text-align: center;" | User defined
| style="text-align: center;" | HP
(1.2 - 1.8V)
| style="text-align: center;" | User defined
|}
[1]
*HR = High Range
*HP = High Performance
==Connectors pinout =BoraXEVB voltage selection settings===BoraXEVB provides several configuration jumpers that allow to easily select the voltages used for PL's I/O banks. The following tables lists some of the allowed combinations used to select the most common voltage values. There are other combination available. However, '''some of them are not allowed and may cause permanent hardware damages to the Zynq part'''.
Since characteristics === J1,J2 and J3 ===The pinout of PL's I/O banks differ between Zynq 7015 the J1, J2 and 7030 parts, J3 connectors of the valid combinations '''are not Bora Xpress EVB is the same for all of the BoraX models'''. Please refer to the following sections for more details.====Zynq 7030-based SOMs [[Pinout (default option for BXELKBORAXpress)====|counterpart connectors on BORA Xpress module]].
====Zynq 7015Power supply -based SOMs=JP2 ===
==Block Diagram==Power is provided through the JP2 connector.
The following picture shows BORA Xpress EVB block diagram: JP2 connector is a standard 2.1mm/5.5mm DC power jack with positive center pin
[[File{| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|1 || VIN || Power supply || Nominal:Boraxevb+12V|-block_diagram.png|2 , 3 |thumb|centerDGND |600px|BoraXEVB simplified block diagram]]Ground || -===Configurable routing options===|-FPGA banks #12, #34 and #35 supports different routing options as shown in the following picture. |}
For a detailed description of FMC connector routing, please refer to [[#FPGA Mezzanine Card (FMC) Connector === Boot mode selection - J27|this section]].[[File:Boraxevb-FPGA-signals-routing.png|thumb|center|600px|Configurable routing options diagram]]S5 ===
== Features ==S5 is a dip-switch for the boot mode selection. The following table reports the available options and the related configurations:
* 10/100/1000 Ethernet #0 (PS){| class="wikitable"* 10/100/1000 Ethernet #1 (Routed through EMIO)|-* 1x USB 2! !! S5.0 OTG (MicroAB connector)* 1x Serial port (RS232 DB9)* 1x MicroSD* 1x FPGA Mezzanine Card (FMC) Connector* XADC** Some signals of Bank 35 can be configured as XADC signals1 !! S5. For this reason they can be routed alternatively to 2!! S5.54mm-pitch connectors, instead of FMC connector3 !! S5.4 !! S5.* State-of-the-art programmable MEMS clock generator (Silicon Labs Si504): this is an alternative clock source to allow the user to easily experiment his/her own peripherals and IPs on FPGA* JTAG port* Socket for [[Wireless_Module_(DWM) | DWM Wireless Module]]* Digilent Pmod™ Compatible expansion connectors* Headers for external for NAND flash and SPI NOR flash* 25 !! S5.54mm-pitch pin-strip connectors for Bora Xpress PS and PL configurable peripherals (MIO and EMIO interfaces, GPIOs, custom IPs, 6 !! S5.7 !! S5.)* Jumpers for voltage selection of the PL banks* +12V power connector == Known limitations == Board version CS040713A has the following limitations: {| class="wikitable" 8
|-
!Issue!Description| SPI-NOR || OFF || ON || OFF || ON || ON || ON || ON || OFF
|-
| LCD_BKLT_PWM I/O voltageSD-card | LCD_BKLT_PWM signal is derived from IO_0_13 on BANK13. In the case of LVDS signals for LCD the BANK 13 must be powered at 2.5V. So in this case LCD_BKLT_PWM is an LVCMOS 2.5V signal. It is recommended to place a voltage level translator to 3.3V if the signal voltages are not compatible with the LCD diplay backlight input.| OFF || ON || OFF || ON || ON || OFF || ON || OFF
|-
| FMC connectorNAND | For the [[Product_serial_number|serial numbers]] included in the range EVBBX0000C0R00A0 - EVBBX0000C0R00AB, the connector that is actually mounted on the board is the LPC version, not the HPC version listed in the specifications.OFF || ON || OFF || ON || ON || OFF || ON || ON
|-
| JTAG || OFF || ON || OFF || ON || ON || ON || ON || ON
|}
== Connectors pinout =WatchDog Settings - S1, S2 and S3 ===S1, S2 and S3 are dip-switch to override the default startup delay and timeout of the BORA Xpress module watchdog.For more details please refer to [[Watchdog (BORAXpress)|this page]].
=== J1,J2 and J3 ===The pinout of the J1, J2 and J3 connectors of the Bora Xpress EVB is the same of the [[Pinout (BORAXpress)|counterpart connectors on BORA Xpress module]]. === Power supply - JP2 === Power is provided through the JP2 connector. JP2 connector is a standard 2.1mm/5.5mm DC power jack with positive center pin {| class="wikitable"
|-
!Pin# !Pin name!FunctionS1.1 !Notes! S1.2
|-
|1 WD_SET0 SOM default || VIN OFF || Power supply || Nominal: +12VOFF
|-
|2 , 3 WD_SET0 = '1' || DGND ON || Ground || -OFF
|-
| WD_SET0 = '0' || OFF || ON
|}
=== Boot mode selection - S5 === S5 is a dip-switch for the boot mode selection. The following table reports the available options and the related configurations: {| class="wikitable"|-! !! S2.1 !! S2.2
|-
! !! S5.1 !! S5.2 !! S5.3 !! S5.4 !! S5.5 !! S5.6 !! S5.7 !! S5.8| WD_SET1 SOM default || OFF || OFF
|-
| SPI-NOR || OFF || ON || OFF || ON || ON || ON WD_SET1 = '1' || ON || OFF
|-
| SD-card WD_SET1 = '0' || OFF || ON || OFF || ON || ON || OFF || ON || OFF|-| NAND || OFF || ON || OFF || ON || ON || OFF || ON || ON|-| JTAG || OFF || ON || OFF || ON || ON || ON || ON || ON
|}
=== WatchDog Settings - S1, S2 and S3 ===
S1, S2 and S3 are dip-switch to override the default startup delay and timeout of the BORA Xpress module watchdog.
For more details please refer to [[Watchdog (BORAXpress)|this page]].
{| class="wikitable"
|-
! !! S1S3.1 !! S1S3.2
|-
| WD_SET0 WD_SET2 SOM default || OFF || OFF
|-
| WD_SET0 WD_SET2 = '1' || ON || OFF
|-
| WD_SET0 WD_SET2 = '0' || OFF || ON
|}
{| class="wikitable"|-! !! S2.1 !! S2.2|-| WD_SET1 SOM default || OFF || OFF|-| WD_SET1 = '1' || ON || OFF|-| WD_SET1 = '0' || OFF || ON|} {| class="wikitable"|-! !! S3.1 !! S3.2|-| WD_SET2 SOM default || OFF || OFF|-| WD_SET2 = '1' || ON || OFF|-| WD_SET2 = '0' || OFF || ON|} === Ethernet port #0 (ETH0) - J8 ===
J8 is a RJ45 Gigabit Ethernet connector - incorporating magnetics - connected to the Bora Xpress integrated ethernet controller and PHY.
|-
|}
==PL's I/O voltage selections==
PL's I/O banks voltage can be selected via configuration jumpers. It is worth remembering that:
*'''each bank must be powered even if none of its I/Os is used'''
*'''voltage selection must be done before powering up the board'''.
The following table recaps the characteristics of the PL's I/O banks, in terms of allowable power supplies.
{|class="wikitable" style="text-align: center;"
! rowspan="2" style="text-align: center; font-weight: bold;" | Zynq p/n
! colspan="2" style="text-align: center; font-weight: bold;" | Bank #34
! colspan="2" style="text-align: center; font-weight: bold;" | Bank #13
! colspan="2" style="text-align: center; font-weight: bold;" | Bank #35
|-
| style="text-align: center; font-weight: bold;" | Type [1]
| style="text-align: center; font-weight: bold;" | I/O voltage setting
| style="text-align: center; font-weight: bold;" | Type [1]
| style="text-align: center; font-weight: bold;" | I/O voltage setting
| style="text-align: center; font-weight: bold;" | Type [1]
| style="text-align: center; font-weight: bold;" | I/O voltage setting
|-
| style="text-align: center;" | 7015
(CLG485 package)
| style="text-align: center;" | HR
(1.2 - 3.3V)
| style="text-align: center;" | User defined
| style="text-align: center;" | HR
(1.2 - 3.3V)
| style="text-align: center;" | User defined
| style="text-align: center;" | HR
(1.2 - 3.3V)
| style="text-align: center;" | User defined
|-
| style="text-align: center;" | 7030
(SBG485 package)
| style="text-align: center;" | HP
(1.2 - 1.8V)
| style="text-align: center;" | User defined
| style="text-align: center;" | HR
(1.2 - 3.3V)
| style="text-align: center;" | User defined
| style="text-align: center;" | HP
(1.2 - 1.8V)
| style="text-align: center;" | User defined
|}
[1]
*HR = High Range
*HP = High Performance
===BoraXEVB voltage selection settings===
BoraXEVB provides several configuration jumpers that allow to easily select the voltages used for PL's I/O banks. The following tables lists some of the allowed combinations used to select the most common voltage values. There are other combination available. However, '''some of them are not allowed and may cause permanent hardware damages to the Zynq part'''.
Since characteristics of PL's I/O banks differ between Zynq 7015 and 7030 parts, the valid combinations '''are not the same for all of the BoraX models'''. Please refer to the following sections for more details.
====Zynq 7030-based SOMs (default option for BXELK)====
====Zynq 7015-based SOMs====
==Schematics==
