Changes

Jump to: navigation, search

Programmable logic (Bora)

57 bytes added, 07:43, 4 October 2016
Introduction
|-
!FPGA Bank
!Type
!I/O Voltage
!Voltage Pins
|-
|Bank 35
|High range (HR)
|User defined<br>VIO=FPGA_VDDIO_BANK35<br>'''1.8 to 3.3V'''
|J1.2<br>J1.66<br>J1.67<br>J1.68
|-
|Bank 34
|High range (HR)
|Fixed<br>'''VIO=3.3 V'''
| -
|-
|Bank 13
|High range (HR)
|User defined<br>VIO=FPGA_VDDIO_BANK13<br>'''1.8 to 3.3V'''
|J3.95<br>J3.96<br>J3.97<br>J3.98<br>J3.99
4,650
edits

Navigation menu