767
edits
Changes
→Feature Summary
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| Debug|| JTAG IEEE 1149.1 Test Access Port<br>ETM port ||
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| PCI Express|| One PCI Express 2.0 lane with integrated PHY <br> (5.0 GT/s Endpoint/Root Complex operations) ||
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|+ align="bottom" style="caption-side: bottom" | Table: Peripherals
