Changes

Category:AxelUltra

5 bytes added, 11:56, 29 September 2016

→‎Feature Summary

| Debug||JTAG IEEE 1149.1 Test Access Port<br>CoreSight™ and Program Trace Macrocell (PTM) ||

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| PCI Express || One PCI Express 2.0 lane with integrated PHY <br> (5.0 GT/s Endpoint/Root Complex operations) ||

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|+ align="bottom" style="caption-side: bottom" | Table: Peripherals

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