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==Block Diagram==
The following picture shows Bora BORA Xpress EVB block diagram:
[[File:Boraxevb-block_diagram.png|thumb|center|600px|BoraXEVB simplified block diagram]]
* 2.54mm-pitch 10x2 header (ARM standard): http://www2.lauterbach.com/pdf/arm_app_jtag.pdf
* This port is connected to Zynq's native JTAG signals. Please note that Zynq's internal JTAG chain supports differents configurations, depending on bootstrap signals. In case split mode is selected, CPU JTAG can be routed separately via PL. For more details please refer to Zynq Technical Reference Manual.
* JTAG on Bora BORA Xpress EVB is also connected to the FMC connector. For more details on how to connect JTAG on a custom FMC card please refer to ANSI/VITA FPGA Mezzanine Card (FMC) Standard.
==== JTAG XILINX - J13 ====
=== USB OTG - J19 ===
J19 is a standard USB MICRO AB connector. It is connected to the Bora BORA Xpress USB 2.0 OTG peripheral. The following table reports the pinout of the connector:
{| class="wikitable"
=== MicroSD - J21 ===
J21 is a microSD memory card connector. It is connected to the Bora BORA Xpress SOM through a bidirectional 1.8V/3.3V voltage-level translator mounted on the Bora BORA Xpress EVB. Level shifter is required because MIO signals are 1.8V. The following table reports the pinout of the connector:
{| class="wikitable"
=== DWM (DAVE Wifi/BT module) socket - J23 ===
J23 is a 52991-0308 connector type (30 pins, vertical, 0.50mm picth). This socket connects the [[Wireless_Module_(DWM) | DWM Wireless Module]] (optional) to the Bora BORA Xpress EVB. The following table reports the pinout of the connector:
{| class="wikitable"
=== CAN - J24 ===
J24 is a 10-pin 5x2x2.54mm pitch vertical header directly connected to Bora BORA Xpress SoM's transceiver for the CAN interface. This 2.5mm-pitch header is compatible with commonly available IDC-10/DB9 flat cables. The following table reports the pinout of the connector:
{| class="wikitable"
=== Touch screen - J25===
J25 is a ZIF 4-pin 1.0mm pitch connector that connects the touchscreen drive lines to the touch screen controller on the Bora BoORA Xpress EVB. The following table reports the pinout of the connector:
{| class="wikitable"
* partially compliant to FMC HPC because HPC side is not fully populated.
The following tables detail how BoraX BORA Xpress signals have been routed to FMC connector. At this [[:File:BoraXEVB-FMC-routing.zip|link]] a spreadsheet providing the same information is available for download.
==== HPC Row A ====
** Silicon Labs Si571 programmable clock generator: this clock si connected to PL to allow the user to easily experiment his/her own peripherals and IPs on FPGA
** resistive touch screen controller for LCD screen
** consumption monitor: this is connected to shunt resistor put in series on Bora BORA power rail, allowing to measure SoM consumption
==== ADC - JP30, JP31, JP32 ====
